公开(公告)号：US20220282437A1

公开(公告)日：2022-09-08

申请号：US17192393

申请日：2021-03-04

Applicant: Nolda Ray Allen

Inventor： Nolda Ray Allen

IPC: E01F9/669 ,  E01F15/06 ,  E01F9/619

Abstract: A cable barrier delineator for selective attachment on roadway barrier cable systems that utilize steel cables between posts as a vehicle safety barrier along highways. The cable barrier delineator is a rectangular one-piece cable attachment having double sided reflective insert surfaces with a split apertured mounting tab for cable engagement extending therefrom. An attachment tab retainment tie stays selectively positioned through apertures in said mounting tabs, stabilizes and prevent unauthorized removal once installed and secured on the cable.

公开(公告)号：US07342212B2

公开(公告)日：2008-03-11

申请号：US11395193

申请日：2006-03-31

Applicant: Ray Allen Mentzer ,  Frank J. DeMonte ,  Jeffery Steven Beck ,  Matthew Michael Borg ,  Charles Grant Myers

Inventor： Ray Allen Mentzer ,  Frank J. DeMonte ,  Jeffery Steven Beck ,  Matthew Michael Borg ,  Charles Grant Myers

IPC: H01L27/00 ,  G01J1/44 ,  H01J40/14 ,  H03F3/08

CPC classification number: H04N9/045 ,  H04N5/374 ,  H04N5/378

Abstract: An active pixel sensor (APS) image sensor comprises an array of pixel circuits corresponding to rows and columns of pixels, a plurality of amplifiers that buffer signals output by the array of pixel circuits, and a plurality of sample and hold circuits that read the buffered signals. A routing mechanism is positioned between the array of pixel circuits and the plurality of amplifiers. A controller selects a set of the pixel circuits for sampling and is configured to control the routing mechanism to couple each pixel circuit in the set to a different one of the amplifiers during a normal mode of operation and to couple each pixel circuit of a subset of pixel circuits in a first set of pixel circuits to a different amplifier of a first subset of the amplifiers, to couple each pixel circuit of a subset of pixel circuits in a second set of pixel circuits to a different amplifier of a second subset of the amplifiers, and to connect the amplifiers of the first and second subsets of amplifiers in pairs to a common one of the sample and hold circuits during a sub-sampling mode of operation.

Abstract translation: 有源像素传感器（APS）图像传感器包括对应于像素行和列的像素电路阵列，缓冲由像素电路阵列输出的信号的多个放大器以及读取缓冲的多个采样和保持电路 信号。 路由机制位于像素电路阵列和多个放大器之间。 控制器选择一组用于采样的像素电路，并且被配置为控制路由机制以在正常操作模式期间将集合中的每个像素电路耦合到不同的一个放大器，并且将 将第一组像素电路中的像素电路连接到放大器的第一子集的不同放大器，以将第二组像素电路中的像素电路的子集的每个像素电路耦合到放大器的第二子集的不同放大器 并且在子采样操作模式期间将放大器的第一和第二子集的放大器成对连接到采样和保持电路中的公共一个。

公开(公告)号：US5973516A

公开(公告)日：1999-10-26

申请号：US139011

申请日：1998-08-24

Applicant: Duncan James Bremner ,  Ray Allen Reed

Inventor： Duncan James Bremner ,  Ray Allen Reed

IPC: H03K5/1534 ,  H04M3/22 ,  H03K5/153

CPC classification number: H03K5/1534 ,  H04M3/2272

Abstract: A subscriber line interface circuit which includes a transient signal detector with temporal hysteresis. During steady state operation, the drive current for the subscriber loop allows the loop to respond to changes in loop conditions according to a steady state time constant of the loop filter. Upon detection of a line voltage transient which exceeds a predetermined threshold in either a positive or negative direction, the filter time constant is significantly reduced (e.g., 100:1) and held at such reduced value following the initial transient and for a predetermined time period after the line voltage has fallen back below such predetermined threshold. This allows the transient conditions to be fully compensated prior to resetting the filter time constant back from the lower transient value to the higher steady state value.

Abstract translation: 一种用户线接口电路，其包括具有时滞的瞬态信号检测器。 在稳态操作期间，用户环路的驱动电流允许环路根据环路滤波器的稳态时间常数响应环路条件的变化。 在正或负方向上检测到超过预定阈值的线路电压瞬变时，滤波器时间常数显着降低（例如，100:1），并且在初始瞬变之后保持在这样的减小值，并且在预定时间段 在线路电压下降到低于该预定阈值之后。 这使得在将滤波器时间常数从较低的瞬态值恢复到较高的稳态值之前，可以完全补偿瞬态条件。

公开(公告)号：US5938737A

公开(公告)日：1999-08-17

申请号：US799352

申请日：1997-02-14

Applicant: Joseph Smallcomb ,  Ray Allen Daniel

Inventor： Joseph Smallcomb ,  Ray Allen Daniel

IPC: G06F13/00 ,  H03M7/30 ,  H04L29/06 ,  G06F13/38 ,  G06F15/17

CPC classification number: H03M7/30 ,  H04L29/06 ,  H04L69/04

Abstract: Interactive internet activities are a very popular means for gathering information for business, personal, medical, entertainment and other purposes. Most internet interaction is asymmetrical in nature in that a client's requests for information are much smaller (in data size) than the resulting information delivered by the server. Although the client/internet link is inherently asymmetrical, there remains a great deal of interaction and overhead required between the client and the server that increases the bandwidth needs for the client's upstream request channel. There are many advantages to reducing this upstream traffic volume and thereby making the internet interaction even more asymmetrical. Such compression of request data could allow more clients to utilize a single upstream data path instead of separate paths.

公开(公告)号：US5874931A

公开(公告)日：1999-02-23

申请号：US671962

申请日：1996-06-28

Applicant: Rodney Drake ,  Ray Allen

Inventor： Rodney Drake ,  Ray Allen

IPC: G02F1/133 ,  G06F3/147 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

CPC classification number: G06F3/147 ,  G09G3/18 ,  G09G3/3696

Abstract: A single semiconductor chip device is utilized for controlling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch. Consequently, data in each master storage latch may be changed periodically by the CPU without interference with downloading of updated data from the single slave storage unit.

Abstract translation: 单个半导体芯片装置用于控制具有与其相关联的液晶显示器（LCD）的外部系统。 双端口随机存取存储器（RAM）存储表示要显示在LCD上的信息的数据。 RAM包括多个主数据存储锁存器和由所有多个主存储锁存器共享的单个从属数据存储锁存器。 微控制器具有中央处理单元（CPU），用于经由一个RAM端口与主存储锁存器进行通信，以周期性地改变存储在其中的数据。 LCD控制模块使用来自每个主存储锁存器的数据连续地更新单个从存储锁存器中的数据，并且在从主存储器锁存器每次更新之后将更新的数据从单个从存储锁存器下载到与LCD相关联的临时存储器 并在更新下一个主存储锁存器的数据之前。 因此，每个主存储锁存器中的数据可以由CPU周期性地改变，而不会干扰来自单个从存储单元的更新数据的下载。

公开(公告)号：US5667021A

公开(公告)日：1997-09-16

申请号：US542441

申请日：1995-10-12

Applicant: Vance Allen Bailey ,  Monte Reeves Highsmith ,  Ray Allen Highsmith ,  Stephen Joseph Bailey

Inventor： Vance Allen Bailey ,  Monte Reeves Highsmith ,  Ray Allen Highsmith ,  Stephen Joseph Bailey

IPC: E02D7/06 ,  E04H17/26 ,  B25D17/00

CPC classification number: E02D7/06 ,  E04H17/263

Abstract: A grade stake driver includes a frame for supporting a hammer and a grade stake under the hammer. A shuttle secured to the hammer movably mounts onto the frame to connect the hammer to the frame. A hoist secured to the shuttle mounts onto the frame to permit the raising and lowering of the hammer. A receiver mounted on the frame outputs a control signal in response to a transmitted signal. A switch mounted on the frame transforms the control signal into an on/off signal. A relay mounted on the frame connects the hammer to a power source in response to the on/off signal, thereby effecting the driving of the grade stake.

Abstract translation: 级别的利益相关者包括用于支撑锤子的锤架和在锤下的等级桩。 固定到锤的梭子可移动地安装在框架上以将锤连接到框架。 固定在梭子上的提升机安装在框架上，以允许锤子的升高和降低。 安装在框架上的接收器响应于发送的信号输出控制信号。 安装在框架上的开关将控制信号转换成开/关信号。 安装在框架上的继电器响应于开/关信号将锤连接到电源，从而实现等级桩的驱动。

公开(公告)号：US5647850A

公开(公告)日：1997-07-15

申请号：US353809

申请日：1995-03-15

Applicant: William Ray Allen

Inventor： William Ray Allen

IPC: A61B5/022 ,  A61B17/135 ,  A61H1/00

CPC classification number: A61B5/02233 ,  A61B17/135 ,  A61M5/427 ,  Y10S128/20

Abstract: The invention described herein is a method and apparatus for vein location. The apparatus includes a vein locating device composed an inflatable bladder attached between two covers and including a holding straps for attaching the device to a limb of a human patient. The method described herein sets for the steps of placing the apparatus on the limb of a human patient and inflating the device so as to constrict veins in a desired area so as to permit the location of a particular vein or veins.

Abstract translation: 本文描述的本发明是用于静脉位置的方法和装置。 该装置包括一个静脉定位装置，该静脉定位装置构成一个连接在两个盖子之间的可充气气囊，并包括用于将装置连接到人类患者肢体的保持带。 本文描述的方法设置了将装置放置在人类患者的肢体上并使装置膨胀以便收缩期望区域中的静脉的步骤，以允许特定静脉或静脉的位置。

公开(公告)号：US5473758A

公开(公告)日：1995-12-05

申请号：US938911

申请日：1992-08-31

Applicant: Ray Allen ,  Sumit Mitra ,  Rodney Drake

Inventor： Ray Allen ,  Sumit Mitra ,  Rodney Drake

IPC: G11C16/10 ,  G06F15/02

CPC classification number: G11C16/102

Abstract: A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

Abstract translation: 在单个半导体芯片中制造微控制器和相关联的EPROM程序存储器。 微控制器设备适于在使用要由设备控制的系统安装设备的电路中的数字命令字或其他位模式中使用数字命令字或其他位模式进行编程，并将其编程引脚与系统隔离以避免对 系统运行时正在进行编程。 在线编程使用量远低于设备的输入/输出（I / O）引脚总数，总共少于命令字中的位数。 这是通过引脚和程序存储器之间的串行/并行编程接口实现的，并且通过将数据以串行方式应用于其被锁存并且并行加载到存储器中的接口来实现。 输入到设备的数据可以替代地以与字节相同的字节并行输入，该字节的宽度小于设备的I / O引脚的总数。

公开(公告)号：US5351216A

公开(公告)日：1994-09-27

申请号：US26908

申请日：1993-03-05

Applicant: Tom Salt ,  Rodney Drake ,  Ray Allen

Inventor： Tom Salt ,  Rodney Drake ,  Ray Allen

IPC: G05B19/042 ,  G06F11/14 ,  G11C16/22 ,  G06K5/00

CPC classification number: G05B19/0428 ,  G06F11/1402 ,  G11C16/22 ,  G05B2219/23215 ,  G05B2219/23345 ,  G05B2219/25301

Abstract: A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

Abstract translation: 单芯片半导体微控制器装置适于控制外部系统的操作的一个方面。 该装置包括CPU，用于存储由CPU选择性地执行以执行控制功能的指令的程序存储器，以及适于被写入以便将选择的数据存储在数据存储器的多个地址中的选定数据中的外围EEPROM数据存储器 并且用于在其控制功能内由CPU选择性地检索存储的水坝。 器件的内部逻辑被实现为在器件的异步复位发生时中止EEPROM数据存储器上正在进行的写入操作。 由逻辑设置错误标志以指示写入操作正在中止，并且在写入操作中止时部分写入EEPROM存储器的数据保持不变。

公开(公告)号：US3973903A

公开(公告)日：1976-08-10

申请号：US448363

申请日：1974-03-05

Applicant: Ray Allen Clarke

Inventor： Ray Allen Clarke

IPC: C09B26/04 ,  C08J3/20

CPC classification number: C09B26/04 ,  Y10S8/919

Abstract: A process for making yellow, basic azomethine dyes for paper, leather and textiles, and concentrated, stable solutions thereof; the process being an improvement in the process of reacting an azo dye base precursor of the formula ##SPC1##Wherein A is phenyl or substituted phenyl, with dimethyl sulfate in solution, and in the presence of an acid-binding agent,THE IMPROVEMENT COMPRISING EMPLOYING AN AQUEOUS SOLUTION HAVING AT LEAST 30 WEIGHT PERCENT WATER, EMPLOYING DIMETHYL SULFATE IN A MOLAR EXCESS OF FROM 100% TO 300%, AND EMPLOYING FROM 2.0 TO 3.5 MOLES OF MAGNESIUM OXIDE AS THE ACID-BINDING AGENT PER MOLE OF PRECURSOR.

Abstract translation: 制造用于纸，皮革和纺织品的黄色碱性偶氮甲碱染料及其浓缩的稳定溶液的方法; 该方法是使式WHEREIN A为苯基或取代的苯基的偶氮染料基前体与溶液中的硫酸二甲酯以及在酸结合剂的存在下反应的方法的改进。包含使用水性溶液的改进 至少30重量百分比的水，在100％至300％的摩尔过量中使用二甲基硫酸盐，并从2.0至3.5摩尔的氧化镁作为前驱体的酸性粘合剂。