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    Premature termination of microcontroller EEPROM write
    1.
    发明授权
    Premature termination of microcontroller EEPROM write 失效
    微控制器EEPROM过早终止写入

    公开(公告)号：US5351216A

    公开(公告)日：1994-09-27

    申请号：US26908

    申请日：1993-03-05

    Applicant: Tom Salt ,  Rodney Drake ,  Ray Allen

    Inventor： Tom Salt ,  Rodney Drake ,  Ray Allen

    IPC: G05B19/042 ,  G06F11/14 ,  G11C16/22 ,  G06K5/00

    CPC classification number: G05B19/0428 ,  G06F11/1402 ,  G11C16/22 ,  G05B2219/23215 ,  G05B2219/23345 ,  G05B2219/25301

    Abstract: A single chip, semiconductor microcontroller device is adapted to control an aspect of the operation of an external system. The device includes a CPU, program memory for storing instructions to be selectively executed by the CPU to perform the control functions, and peripheral EEPROM data memory adapted to be written to for storing selected data in selected ones of a multiplicity of addresses of the data memory and for selective retrieval of the stored dam by the CPU within its control function. Internal logic in the device is implemented to abort a write operation in progress on the EEPROM data memory upon occurrence of an asynchronous reset of the device. An error flag is set by the logic to indicate that the write operation is being aborted, and the data that was partially written to the EEPROM memory at the time the write operation was aborted is held intact.

    Abstract translation: 单芯片半导体微控制器装置适于控制外部系统的操作的一个方面。 该装置包括CPU，用于存储由CPU选择性地执行以执行控制功能的指令的程序存储器，以及适于被写入以便将选择的数据存储在数据存储器的多个地址中的选定数据中的外围EEPROM数据存储器 并且用于在其控制功能内由CPU选择性地检索存储的水坝。 器件的内部逻辑被实现为在器件的异步复位发生时中止EEPROM数据存储器上正在进行的写入操作。 由逻辑设置错误标志以指示写入操作正在中止，并且在写入操作中止时部分写入EEPROM存储器的数据保持不变。

    Code protection in microcontroller with EEPROM fuses
    2.
    发明授权
    Code protection in microcontroller with EEPROM fuses 失效
    具有EEPROM保险丝的微控制器中的代码保护

    公开(公告)号：US5469557A

    公开(公告)日：1995-11-21

    申请号：US26967

    申请日：1993-03-05

    Applicant: Tom Salt ,  Rodney Drake

    Inventor： Tom Salt ,  Rodney Drake

    IPC: G11C8/20 ,  G11C16/22 ,  G06F12/14 ,  H04L9/00

    CPC classification number: G11C8/20 ,  G11C16/22

    Abstract: A semiconductor microcontroller device is adapted to control the operation of an external system. The device includes a CPU, program memory for storing instructions to be executed by the CPU to perform its control functions, and data memory for storing data for selective retrieval by the CPU. The contents of either memory are code protected by an EEPROM fuse, and are automatically erased if the code protect state of the EEPROM fuse is sought to be reset, and the EEPROM fuse is reset only after the erasure of the memory contents.

    Abstract translation: 半导体微控制器装置适于控制外部系统的操作。 该设备包括CPU，用于存储要由CPU执行以执行其控制功能的指令的程序存储器，以及用于存储用于CPU选择性检索的数据的数据存储器。 任何一个存储器的内容均由EEPROM保险丝进行代码保护，如果要求复位EEPROM保险丝的代码保护状态，并且只有擦除存储器内容之后EEPROM保险丝才会被复位。

    Microcontroller with dual port ram for LCD display and sharing of slave ports
    3.
    发明授权
    Microcontroller with dual port ram for LCD display and sharing of slave ports 失效
    具有双端口RAM的微控制器，用于LCD显示和从站端口的共享

    公开(公告)号：US5874931A

    公开(公告)日：1999-02-23

    申请号：US671962

    申请日：1996-06-28

    Applicant: Rodney Drake ,  Ray Allen

    Inventor： Rodney Drake ,  Ray Allen

    IPC: G02F1/133 ,  G06F3/147 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

    CPC classification number: G06F3/147 ,  G09G3/18 ,  G09G3/3696

    Abstract: A single semiconductor chip device is utilized for controlling an external system which has a liquid crystal display (LCD) associated therewith. A dual port random access memory (RAM) stores data representative of information to be displayed on the LCD. The RAM includes a plurality of master data storage latches and a single slave data storage latch shared by all of the plurality of master storage latches. A microcontroller has a central processing unit (CPU) for communicating with the master storage latches via one of the RAM ports to periodically change the data stored therein. An LCD control module successively updates the data in the single slave storage latch with data from each of the master storage latches and downloads the updated data from the single slave storage latch to a temporary store associated with the LCD after each update from a master storage latch and before the update of data from the next master storage latch. Consequently, data in each master storage latch may be changed periodically by the CPU without interference with downloading of updated data from the single slave storage unit.

    Abstract translation: 单个半导体芯片装置用于控制具有与其相关联的液晶显示器（LCD）的外部系统。 双端口随机存取存储器（RAM）存储表示要显示在LCD上的信息的数据。 RAM包括多个主数据存储锁存器和由所有多个主存储锁存器共享的单个从属数据存储锁存器。 微控制器具有中央处理单元（CPU），用于经由一个RAM端口与主存储锁存器进行通信，以周期性地改变存储在其中的数据。 LCD控制模块使用来自每个主存储锁存器的数据连续地更新单个从存储锁存器中的数据，并且在从主存储器锁存器每次更新之后将更新的数据从单个从存储锁存器下载到与LCD相关联的临时存储器 并在更新下一个主存储锁存器的数据之前。 因此，每个主存储锁存器中的数据可以由CPU周期性地改变，而不会干扰来自单个从存储单元的更新数据的下载。

    System having input output pins shifting between programming mode and normal mode to program memory without dedicating input output pins for programming mode
    4.
    发明授权
    System having input output pins shifting between programming mode and normal mode to program memory without dedicating input output pins for programming mode 失效
    具有输入输出引脚在编程模式和正常模式之间切换到程序存储器的系统，而不用将输入输出引脚用于编程模式

    公开(公告)号：US5473758A

    公开(公告)日：1995-12-05

    申请号：US938911

    申请日：1992-08-31

    Applicant: Ray Allen ,  Sumit Mitra ,  Rodney Drake

    Inventor： Ray Allen ,  Sumit Mitra ,  Rodney Drake

    IPC: G11C16/10 ,  G06F15/02

    CPC classification number: G11C16/102

    Abstract: A microcontroller and associated EPROM program memory are fabricated in a single semiconductor chip. The microcontroller device is adapted to be programmed using digital command words or other bit patterns applied as inputs after installation of the device in circuit with a system to be controlled by the device, and to have its programming pins isolated from the system to avoid effects on system operation while the programming is taking place. The in-circuit programming uses considerably less than the total number of input/output (I/O) pins of the device, which in total are fewer than the number of bits in a command word. This is achieved with a serial/parallel programming interface between the pins and the program memory, and by applying the data in serial fashion to the interface where it is latched and loaded in parallel in the memory. Input data to the device may alternatively be entered in parallel to the interface in bytes of width less than the total number of I/O pins of the device.

    Abstract translation: 在单个半导体芯片中制造微控制器和相关联的EPROM程序存储器。 微控制器设备适于在使用要由设备控制的系统安装设备的电路中的数字命令字或其他位模式中使用数字命令字或其他位模式进行编程，并将其编程引脚与系统隔离以避免对 系统运行时正在进行编程。 在线编程使用量远低于设备的输入/输出（I / O）引脚总数，总共少于命令字中的位数。 这是通过引脚和程序存储器之间的串行/并行编程接口实现的，并且通过将数据以串行方式应用于其被锁存并且并行加载到存储器中的接口来实现。 输入到设备的数据可以替代地以与字节相同的字节并行输入，该字节的宽度小于设备的I / O引脚的总数。

    Functional pathway configuration at a system/IC interface
    6.
    发明授权
    Functional pathway configuration at a system/IC interface 失效
    功能通道在系统/ IC接口配置

    公开(公告)号：US06552567B1

    公开(公告)日：2003-04-22

    申请号：US09964664

    申请日：2001-09-28

    Applicant: Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

    Inventor： Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

    IPC: H03K190175

    CPC classification number: G06F15/76

    Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

    Abstract translation: 本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。 更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。 更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。

    Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation
    7.
    发明授权
    Microcontroller with LCD control over updating of RAM-stored data determines LCD pixel activation 失效
    具有LCD控制的微控制器可更新RAM存储数据，从而确定LCD像素激活

    公开(公告)号：US6031510A

    公开(公告)日：2000-02-29

    申请号：US671950

    申请日：1996-06-28

    Applicant: Rodney Drake ,  Scott Ellison

    Inventor： Rodney Drake ,  Scott Ellison

    IPC: G02F1/133 ,  G09G3/18 ,  G09G3/20 ,  G09G3/36

    CPC classification number: G09G3/18 ,  G09G2330/02

    Abstract: Method and apparatus for controlling the updating of a random access memory (RAM) that stores data for coding the activation of segments of one or more alphanmeric characters of a liquid crystal display (LCD), to maintain substantially a direct current (DC) voltage value of zero across transparent conductive plates of the LCD, is performed or provided in a microcontroller having internal LCD control capabilities. A type B waveform is employed for activating the LCD, the waveform being of a type in which data is transmitted over two frames, the data in the second frame of which is the inverse of data in the first frame thereof to maintain an average DC voltage value over each two-frame portion of the waveform at substantially zero volt. The RAM is allowed to be written to for updating the data therein only after completion of an entire two-frame portion of the waveform and before commencement of a new two-frame portion, to avoid a non-zero average DC voltage across the LCD glass during a two-frame portion. An error bit is set whenever an attempt is made to write to the RAM at times other than between the end of a two-frame portion and the commencement of a new two-frame portion. A response to the error bit is made by returning to the write step that prompted it, to determine whether all of the data intended to be written has been stored in the RAM.

    Abstract translation: 用于控制随机存取存储器（RAM）的更新的方法和装置，其存储用于对液晶显示器（LCD）的一个或多个字母字符的段的激活进行编码的数据，以维持基本上直流（DC）电压值 在LCD的透明导电板上的零位被执行或提供在具有内部LCD控制能力的微控制器中。 采用B型波形来激活LCD，该波形是数据在两帧上传输的类型，第二帧中的数据是其第一帧中的数据的倒数，以保持平均DC电压 波形的每个两帧部分基本上为零伏。 在完成波形的整个两帧部分之后并且在新的两帧部分开始之前，允许RAM被写入以用于更新其中的数据，以避免LCD玻璃上的非零平均DC电压 在两帧部分。 每当尝试在两帧部分的结束之前的时间和新的两帧部分的开始之间的时间尝试写入RAM时，设置错误位。 通过返回提示它的写入步骤来确定对错误位的响应，以确定所有要写入的数据是否已经存储在RAM中。

    Method for powering down unused configuration bits to minimize power consumption
    8.
    发明授权
    Method for powering down unused configuration bits to minimize power consumption 有权
    关闭未使用配置位以最小化功耗的方法

    公开(公告)号：US06463544B2

    公开(公告)日：2002-10-08

    申请号：US09850214

    申请日：2001-05-07

    Applicant: Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

    Inventor： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

    IPC: G06F126

    CPC classification number: G11C5/14 ,  G11C7/1045 ,  H03K19/0016

    Abstract: A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

    Abstract translation: 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

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