公开(公告)号：US20190148503A1

公开(公告)日：2019-05-16

申请号：US16243564

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok CHOI ,  Hwichan JUN ,  Yoonhae KIM ,  Chulsung KIM ,  Heungsik PARK ,  Doo-Young LEE

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

公开(公告)号：US20240313077A1

公开(公告)日：2024-09-19

申请号：US18537536

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulsung KIM ,  Yeonghan GWON ,  Jinkyung SON ,  Jaepo LIM

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/66439 ,  H01L29/775

Abstract: Disclosed is a semiconductor device comprising a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns that are vertically stacked and spaced apart from each other, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns and including inner electrodes between neighboring semiconductor patterns and an outer electrode on an uppermost semiconductor pattern, and a capping pattern on a top surface of the outer electrode. A line-width of the outer electrode is a first width. The outer electrode has a first height. The first height is equal to or less than the first width.