公开(公告)号：US20250096134A1

公开(公告)日：2025-03-20

申请号：US18650288

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo KIM ,  Hyunwoo KANG ,  Mingyu KIM ,  Wandon KIM ,  Wonkeun CHUNG ,  Hyoseok CHOI

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

公开(公告)号：US20250107179A1

公开(公告)日：2025-03-27

申请号：US18663867

申请日：2024-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun CHUNG ,  Geunwoo KIM ,  Wandon KIM ,  Hyoseok CHOI

IPC: H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Provided is an integrated circuit device and a method of manufacturing same, the integrated circuit device including: a fin-type active region on a substrate, a pair of insulating spacers on the fin-type active region and the substrate and defining a first space, a gate dielectric film contacting the gate line in the first space, a gate contact plug having a conductive bottom surface contacting a top contact portion of the gate line in the first space, and a capping insulating pattern including an insulating bottom surface, a pair of first insulating sidewalls, and a second insulating sidewall, the insulating bottom surface contacting a local top surface of the gate line in the first space, the pair of first insulating sidewalls contacting the pair of insulating spacers, and the second insulating sidewall contacting the gate contact plug, wherein an insulating top surface of the capping insulating pattern and a conductive top surface of the gate contact plug extend along one plane.

公开(公告)号：US20240266257A1

公开(公告)日：2024-08-08

申请号：US18382545

申请日：2023-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin LIM ,  Jinnam KIM ,  Jongmin BAEK ,  Hyoseok CHOI

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having a front surface including an active region and a rear surface opposite to the front surface. An active pattern is on the active region. A gate structure extends in a second direction on the active region. Source/drain regions are disposed on the active pattern on both sides of the gate structure. A front interconnection structure is disposed on the gate structure and the source/drain regions. A rear interconnection structure is disposed on the rear surface of the substrate. A target region defined by the source/drain regions and the active pattern includes a non-oxidizing material at a first concentration. The non-oxidizing material is injected during a high-pressure heat treatment process. A rear interconnection region defined by the substrate, the rear through-structure, and the rear interconnection structure includes the non-oxidizing material at a second concentration higher than the first concentration.

公开(公告)号：US20240250000A1

公开(公告)日：2024-07-25

申请号：US18468317

申请日：2023-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghyuk YIM ,  Wandon KIM ,  Hyunbae LEE ,  Hyoseok CHOI ,  Sunghwan KIM ,  Junki PARK

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate including an active pattern, a source/drain pattern on the active pattern, an active contact on the source/drain pattern; a lower power line in the substrate, a lower contact that vertically connects the active contact to the lower power line, a conductive layer between the lower contact and the lower power line, and a power delivery network layer on a bottom surface of the substrate. The conductive layer may include silicon (Si) and a first element. The first element may include a transition metal or a metalloid. A concentration of the first element may decrease in a direction from the lower contact toward the lower power line.

公开(公告)号：US20190148503A1

公开(公告)日：2019-05-16

申请号：US16243564

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok CHOI ,  Hwichan JUN ,  Yoonhae KIM ,  Chulsung KIM ,  Heungsik PARK ,  Doo-Young LEE

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.