公开(公告)号：US20190148503A1

公开(公告)日：2019-05-16

申请号：US16243564

申请日：2019-01-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoseok CHOI ,  Hwichan JUN ,  Yoonhae KIM ,  Chulsung KIM ,  Heungsik PARK ,  Doo-Young LEE

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

公开(公告)号：US20170358573A1

公开(公告)日：2017-12-14

申请号：US15687929

申请日：2017-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Young LEE ,  Sang-Hyun LEE ,  Myung-Hoon JUNG ,  Do-Hyoung KIM

IPC: H01L27/088 ,  H01L29/45 ,  H01L21/768 ,  H01L29/417 ,  H01L21/28 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28114 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/78

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

公开(公告)号：US20160204030A1

公开(公告)日：2016-07-14

申请号：US14955374

申请日：2015-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： KeunHee BAI ,  Dohyoung KIM ,  Johnsoo KIM ,  Heungsik PARK ,  Doo-Young LEE ,  Sanghyun LEE

IPC: H01L21/768 ,  H01L21/3065 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/517 ,  H01L29/66545

Abstract: A sacrificial layer is formed to cover the gate structures. The sacrificial layer is patterned to form a first opening in the sacrificial layer. A preliminary contact is formed in the first opening and the sacrificial layer is selectively removed. An insulating layer is formed to cover the gate structures and to expose the preliminary contact. The preliminary contact is removed to form a second opening in the insulating layer, and then a contact is formed in the second opening.

Abstract translation: 形成牺牲层以覆盖栅极结构。 牺牲层被图案化以在牺牲层中形成第一开口。 在第一开口中形成初步接触，并且选择性地去除牺牲层。 形成绝缘层以覆盖栅极结构并露出初步接触。 去除预接触以在绝缘层中形成第二开口，然后在第二开口中形成接触。