公开(公告)号：US20210117761A1

公开(公告)日：2021-04-22

申请号：US16857740

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

Inventor： Yuhwan Ro ,  Byeongho KIM ,  Jaehyun Park ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewon CHOI

IPC: G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US20210398597A1

公开(公告)日：2021-12-23

申请号：US17462298

申请日：2021-08-31

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Seungwoo SEO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC: G11C16/30 ,  G06N3/02 ,  G11C5/02 ,  G11C16/10

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

公开(公告)号：US20240243038A1

公开(公告)日：2024-07-18

申请号：US18515384

申请日：2023-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eojin LEE ,  Taehyung KIM ,  Hoyoung TANG ,  Jaehyun LIM

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H10B10/00

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/7851 ,  H10B10/125

Abstract: An integrated circuit includes: a substrate including a cell area and a dummy area, wherein a plurality of cells are arranged in the cell area; a front-side wiring layer arranged over a front surface of the substrate in a vertical direction, wherein the front-side wiring layer includes a first pattern extending in a first direction across the cell area and the dummy area and a second pattern extending in a second direction intersecting the first direction and contacting the first pattern; a through via overlapping the front-side wiring layer in the vertical direction in the dummy area and passing through the substrate; and a back-side wiring layer arranged on a rear surface of the substrate, wherein the back-side wiring layer is connected through the through via and the front-side wiring layer to at least one transistor included in the plurality of cells.

公开(公告)号：US20220374693A1

公开(公告)日：2022-11-24

申请号：US17876136

申请日：2022-07-28

Applicant: Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

Inventor： Yuhwan RO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC: G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F17/16 ,  G06F9/38 ,  G06F9/30

Abstract: A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US20230113482A1

公开(公告)日：2023-04-13

申请号：US17957826

申请日：2022-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eojin LEE ,  Daeyoung Moon ,  Hoyoung Tang ,  Taehyung Kim

IPC: H01L27/11 ,  G11C11/412 ,  G11C8/16

Abstract: A dual-port static random access memory (SRAM) cell is provided. The dual-port SRAM cell includes: P-type active patterns that are spaced apart from one another along a first direction, each of the P-type active patterns extending in a second direction perpendicular to the first direction and including at least one transistor. The P-type active patterns include first through sixth P-type active patterns which are sequentially arranged along the first direction. A first cutting area is provided between the second P-type active pattern and a first boundary of the dual-port SRAM cell that extends along the first direction, and a second cutting area is provided between the fifth P-type active pattern and a second boundary that is opposite to the first boundary and extends along the first direction.

公开(公告)号：US20210110876A1

公开(公告)日：2021-04-15

申请号：US16833864

申请日：2020-03-30

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Seungwoo SEO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC: G11C16/30 ,  G11C5/02 ,  G11C16/10 ,  G06N3/02

Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.