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公开(公告)号：US11973035B2
公开(公告)日：2024-04-30
申请号：US18135766
申请日：2023-04-18
发明人： Ha-Min Hwang , Jong Soo Kim , Ju-Young Lim , Won Seok Cho
IPC分类号： H01L23/535 , H01L21/768 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76895 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
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公开(公告)号：US11652056B2
公开(公告)日：2023-05-16
申请号：US17488727
申请日：2021-09-29
发明人： Ha-Min Hwang , Jong Soo Kim , Ju-Young Lim , Won Seok Cho
IPC分类号： H01L25/065 , H01L23/535 , H01L25/18 , H01L23/00 , H01L21/768
CPC分类号： H01L23/535 , H01L21/76805 , H01L21/76895 , H01L24/08 , H01L25/0657 , H01L25/18 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A semiconductor memory device includes a first substrate including a first region and a second region, a stacked structure only on the first region of the first substrate among the first region and the second region of the first substrate, the stacked structure including word lines, an interlayer insulating film covering the stacked structure, a dummy conductive structure inside the interlayer insulating film, the dummy conductive structure extending through the stacked structure to contact the first substrate, and a plate contact plug inside the interlayer insulating film, the plate contact plug being connected to the second region of the first substrate, and a height of an upper surface of the dummy conductive structure being greater than a height of an upper surface of the plate contact plug relative to an upper surface of the first substrate.
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公开(公告)号：US10242997B2
公开(公告)日：2019-03-26
申请号：US15223255
申请日：2016-07-29
发明人： Chang-Min Choi , Ju-Young Lim , Su-Jin Ahn
IPC分类号： H01L27/108 , H01L27/11582 , H01L27/11556 , H01L27/11573 , H01L27/11565 , H01L27/06 , H01L27/11578 , H01L23/528 , H01L27/1157 , H01L27/11575
摘要： A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.
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公开(公告)号：US11889692B2
公开(公告)日：2024-01-30
申请号：US17349193
申请日：2021-06-16
发明人： Chang-Min Choi , Ju-Young Lim , Su-Jin Ahn
IPC分类号： H01L27/06 , H10B43/27 , H10B41/27 , H10B43/10 , H10B43/20 , H10B43/35 , H10B43/40 , H10B43/50 , H01L23/528
CPC分类号： H10B43/27 , H01L23/5283 , H01L27/0688 , H10B41/27 , H10B43/10 , H10B43/20 , H10B43/35 , H10B43/40 , H10B43/50
摘要： A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.
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公开(公告)号：US11864385B2
公开(公告)日：2024-01-02
申请号：US17718676
申请日：2022-04-12
发明人： Seunghwan Lee , Suhyeong Lee , Ju-Young Lim , Daehyun Jang , Sanghoon Jeong
IPC分类号： H10B43/27 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/41 , H10B43/10 , H10B43/35 , H10B43/40
摘要： Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.
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公开(公告)号：US11469244B2
公开(公告)日：2022-10-11
申请号：US16853838
申请日：2020-04-21
发明人： Seunghwan Lee , Suhyeong Lee , Ju-Young Lim , Daehyun Jang , Sanghoon Jeong
IPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11573 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11529
摘要： Disclosed is a three-dimensional semiconductor memory device comprising intergate dielectric layers and electrode layers alternately stacked on a substrate, a vertical semiconductor pattern that penetrate the intergate dielectric layers and the electrode layers and extends into the substrate, blocking dielectric patterns between the vertical semiconductor pattern and the electrode layers, a tunnel dielectric layer between the blocking dielectric patterns and the vertical semiconductor pattern and in contact with the blocking dielectric patterns and simultaneously with the intergate dielectric layers, and first charge storage patterns between the blocking dielectric patterns and the tunnel dielectric layer. One of the first charge storage patterns is in contact with top and bottom surfaces of one of the blocking dielectric patterns.
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7.发明授权公开(公告)号：US12082412B2
公开(公告)日：2024-09-03
申请号：US17154159
申请日：2021-01-21
发明人： Ju-Young Lim , Jongsoo Kim , Jesuk Moon , Dongwoo Kim , Sunil Shim , Wonseok Cho
摘要： A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, the electrodes including pad portions on the connection region, respectively, and the pad portions of the electrodes being stacked in a staircase structure, first vertical structures penetrating the electrode structure on the cell array region, and second vertical structures penetrating the electrode structure on the connection region, each of the second vertical structures including first parts spaced apart from each other in a first direction, and at least one second part connecting the first parts to each other, the at least one second part penetrating sidewalls of the pad portions, respectively.
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