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公开(公告)号：US09978431B2
公开(公告)日：2018-05-22
申请号：US14819978
申请日：2015-08-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wun-Ki Jung , Min-Ho Kwon , Kwi-Sung Yoo , Won-Ho Choi , Dong-Hun Lee , Seog-Heon Ham
CPC classification number: G11C7/06 , G11C7/10 , G11C7/1033 , G11C7/1051 , G11C7/22 , G11C19/00 , G11C27/02 , H01L27/146 , H01L27/14634 , H01L27/14643
Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.
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公开(公告)号：US09135963B2
公开(公告)日：2015-09-15
申请号：US13757977
申请日：2013-02-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Wun-Ki Jung , Min-Ho Kwon , Kwi-Sung Yoo , Won-Ho Choi , Dong-Hun Lee , Seog-Heon Ham
CPC classification number: G11C7/06 , G11C7/10 , G11C7/1033 , G11C7/1051 , G11C7/22 , G11C19/00 , G11C27/02 , H01L27/146 , H01L27/14634 , H01L27/14643
Abstract: A line memory device includes a plurality of memory cells, a data line pair, a sense amplifier and an output unit. The plurality of memory cells are disposed adjacent to each other in a line. The data line pair is coupled to the memory cells to sequentially transfer memory data bits stored in the memory cells to the sense amplifier. The sense amplifier is configured to amplify the memory data bits that are sequentially transferred through the data line pair by corresponding delay times which are different from each other. The output unit samples an output of the sense amplifier to sequentially output retimed data bits of the memory data bits in response to a read clock signal. The read clock signal has a cyclic period which is less than a maximum delay time among the delay times.
Abstract translation: 行存储器件包括多个存储单元，数据线对，读出放大器和输出单元。 多个存储单元被一行地相邻配置。 数据线对耦合到存储器单元以将存储在存储器单元中的存储器数据位顺序传送到读出放大器。 读出放大器被配置为放大通过数据线对顺序传送的存储器数据位，相应的延迟时间彼此不同。 输出单元对读出放大器的输出进行采样，以响应读取的时钟信号顺序地输出存储器数据位的重新定时数据位。 读取时钟信号具有小于延迟时间之间的最大延迟时间的循环周期。
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公开(公告)号：US09496192B2
公开(公告)日：2016-11-15
申请号：US14326471
申请日：2014-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dae-Lim Kang , Min-Ho Kwon , Wei-Hua Hsu , Sang-Hyun Woo , Hwa-Sung Rhee , Jun-Suk Choi
IPC: H01L27/088 , H01L21/66
CPC classification number: H01L22/34 , H01L27/0886
Abstract: A test pattern of a semiconductor device is provided, which includes first and second fins formed to project from a substrate and arranged to be spaced apart from each other, first and second gate structures formed to cross the first and second fins, respectively, a first source region and a first drain region arranged on the first fin on one side and the other side of the first gate structure, a second source region and a second drain region arranged on the second fin on one side and the other side of the second gate structure, a first conductive pattern connected to the first and second drain regions to apply a first voltage to the first and second drain regions and a second conductive pattern connecting the first source region and the second gate structure to each other.
Abstract translation: 提供了一种半导体器件的测试图案，其包括形成为从衬底突出并布置成彼此间隔开的第一和第二鳍片，分别形成为跨越第一和第二鳍片的第一和第二栅极结构，第一和第二鳍片 源极区域和布置在第一鳍片的第一栅极结构的一侧和另一侧上的第一漏极区域，在第二栅极的一侧和另一侧上布置在第二鳍片上的第二源极区域和第二漏极区域 结构，连接到第一和第二漏极区域以将第一电压施加到第一和第二漏极区域的第一导电图案以及将第一源极区域和第二栅极结构彼此连接的第二导电图案。
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