公开(公告)号：US20240258388A1

公开(公告)日：2024-08-01

申请号：US18537546

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Anthony Dongick LEE ,  Minseung LEE ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.

公开(公告)号：US20250098264A1

公开(公告)日：2025-03-20

申请号：US18604031

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheol NA ,  Beomjin KIM ,  Yoolim AHN ,  Kyoungwoo LEE ,  Minseung LEE ,  Hyeryeong LEE ,  Keun Hwi CHO ,  Seungseok HA

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.