公开(公告)号：US20240194616A1

公开(公告)日：2024-06-13

申请号：US18514054

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Anthony Dongick LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/585 ,  H01L23/481 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：US20240258388A1

公开(公告)日：2024-08-01

申请号：US18537546

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Anthony Dongick LEE ,  Minseung LEE ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.

公开(公告)号：US20240203831A1

公开(公告)日：2024-06-20

申请号：US18486416

申请日：2023-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Jin Kyu KIM ,  Sang Cheol NA ,  Yun Suk NAM ,  Kyoung Woo LEE ,  Hidenobu FUKUTOME

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/528 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/5286 ,  H01L25/18 ,  H10B80/00 ,  H01L24/13

Abstract: A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a power delivery network layer; an insulating layer on the power delivery network layer and having an opening therein; a semiconductor layer filling the opening and covering the insulating layer; a first through-via extending through the semiconductor layer and electrically connected to the power delivery network layer; a second through-via extending through the insulating layer and the semiconductor layer and electrically connected to the power delivery network layer; a logic element on the semiconductor layer and electrically connected to the first through-via; and a passive element on the semiconductor layer and electrically connected to the second through-via.

公开(公告)号：US20230178477A1

公开(公告)日：2023-06-08

申请号：US17866917

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anthony Dongick LEE ,  Sang Cheol NA ,  Seo Woo NAM ,  Ki Chul PARK

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5283 ,  H01L23/53238

Abstract: A semiconductor device is provided. The semiconductor device comprises a first wiring structure which includes a first material, and has a first width on a lowest surface in a first direction and a second wiring structure which includes a second material, is spaced apart from the first wiring structure in the first direction, and has a second width smaller than the first width on a lowest surface in the first direction, wherein a highest surface of the first wiring structure has a third width smaller than the first width in the first direction, and a highest surface of the second wiring structure has a fourth width smaller than the second width in the first direction.

公开(公告)号：US20240339540A1

公开(公告)日：2024-10-10

申请号：US18386898

申请日：2023-11-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Jin KIM ,  Guk Hee KIM ,  Young Woo KIM ,  Jun Soo KIM ,  Sang Cheol NA ,  Kyoung Woo LEE ,  Anthony Dongick LEE ,  Min Seung LEE ,  Myeong Gyoon CHAE ,  Seung Seok HA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7855 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on an upper surface of the substrate, a field insulating layer surrounding a sidewall of the active pattern on the upper surface of the substrate, a first gate electrode extending in a second horizontal direction intersecting the first horizontal direction on the active pattern, a source/drain region disposed on at least one side of the first gate electrode on the active pattern, an upper interlayer insulating layer covering the source/drain region on the field insulating layer, a through via penetrating through the substrate, the field insulating layer and the upper interlayer insulating layer in a vertical direction, the through via spaced apart from the source/drain region in the second horizontal direction, a source/drain contact disposed inside the upper interlayer insulating layer on at least one side of the first gate electrode, the source/drain contact connected to the source/drain region, and a connection portion disposed inside the upper interlayer insulating layer, the connection portion connected to each of the through via and the source/drain contact, wherein a width of the connection portion in the first horizontal direction is greater than a width of the source/drain contact in the first horizontal direction.

公开(公告)号：US20230326831A1

公开(公告)日：2023-10-12

申请号：US18127895

申请日：2023-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheol NA ,  Kyoung Woo LEE ,  Min Chan GWAK ,  Guk Hee KIM ,  Young Woo KIM ,  Anthony Dongick LEE

IPC: H01L23/48 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L29/775 ,  H01L29/423

CPC classification number: H01L23/481 ,  H01L29/66545 ,  H01L29/41733 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: A semiconductor device is provided. The semiconductor device includes: a first substrate; an active pattern extending on the first substrate; a gate electrode extending on the active pattern; a source/drain region on the active pattern; a first interlayer insulating layer on the source/drain region; a sacrificial layer on the first substrate; a lower wiring layer on a lower surface of the sacrificial layer; a through via trench extending to the lower wiring layer by passing through the first interlayer insulating layer and the sacrificial layer in a vertical direction; a through via inside the through via trench and connected to the lower wiring layer; a recess inside the sacrificial layer and protruding from a sidewall of the through via trench in the second horizontal direction; and a through via insulating layer extending along the sidewall of the through via trench and into the recess.

公开(公告)号：US20230170296A1

公开(公告)日：2023-06-01

申请号：US17961056

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Doohwan PARK ,  Kyoungwoo LEE ,  Rakhwan KIM ,  Yoonsuk KIM ,  Jinnam KIM ,  Hoonjoo NA ,  Eunji JUNG ,  Juyoung JUNG

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L23/53238 ,  H01L23/53223 ,  H01L23/53266

Abstract: A semiconductor device includes a substrate. A wiring layer is over the substrate. A first via structure directly contacts a lower portion of the wiring layer. A second via structure directly contacts an upper portion of the wiring layer. The first via structure generates first stress in the wiring layer. The second via structure generates second stress in the wiring layer. The second stress is of an opposite type to the first stress. The first stress and the second stress compensate for each other in the wiring layer.

公开(公告)号：US20230065281A1

公开(公告)日：2023-03-02

申请号：US17751819

申请日：2022-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anthony Dongick LEE ,  Sangcheol NA ,  Kichul PARK ,  Sungyup JUNG ,  Youngwoo CHO

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device including a first insulating structure on a substrate and including a first etch stop layer and a first interlayer insulating layer on the first etch stop layer, a second insulating structure on the first insulating structure and including a second etch stop layer and a second interlayer insulating layer on the second etch stop layer, a conductive line penetrating through the second insulating structure, and extending in a first direction parallel to an upper surface of the substrate, and a plurality of contacts penetrating through the first insulating structure and connected to the conductive line may be provided. The conductive line may include a protrusion extending below the second insulating structure and penetrating through the first interlayer insulating layer to be in contact with the first etch stop layer.