公开(公告)号：US20240194616A1

公开(公告)日：2024-06-13

申请号：US18514054

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Anthony Dongick LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/585 ,  H01L23/481 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：US20200013870A1

公开(公告)日：2020-01-09

申请号：US16418705

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok HA ,  Gukil AN ,  Keun Hwi CHO ,  Sungmin KIM

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.

公开(公告)号：US20240363526A1

公开(公告)日：2024-10-31

申请号：US18421431

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyuhoon CHOI ,  Seungseok HA ,  Seowoo NAM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/544 ,  H10B12/00 ,  H10B41/30 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H01L23/544 ,  H10B12/09 ,  H10B12/50 ,  H10B41/30 ,  H10B41/42 ,  H10B43/30 ,  H10B43/40 ,  H01L2223/54426

Abstract: A semiconductor device according to some example embodiments may include: a substrate having a first region and a second region; a lower interlayer insulating layer on the first region and the second region of the substrate; an upper interlayer insulating layer on the lower interlayer insulating layer; a via structure penetrating through the upper interlayer insulating layer in the first region; a plurality of metal wirings extending in a first direction on the via structure and electrically connected to the via structure; trenches on a same level as that of the via structure and in the upper interlayer insulating layer, in the second region; and a dummy wiring layer having a curved structure along upper surfaces of the trenches, the upper interlayer insulating layer, and the lower interlayer insulating layer.

公开(公告)号：US20240258388A1

公开(公告)日：2024-08-01

申请号：US18537546

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Anthony Dongick LEE ,  Minseung LEE ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.

公开(公告)号：US20250098264A1

公开(公告)日：2025-03-20

申请号：US18604031

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangcheol NA ,  Beomjin KIM ,  Yoolim AHN ,  Kyoungwoo LEE ,  Minseung LEE ,  Hyeryeong LEE ,  Keun Hwi CHO ,  Seungseok HA

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.

公开(公告)号：US20220190136A1

公开(公告)日：2022-06-16

申请号：US17686504

申请日：2022-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungseok HA ,  Gukil AN ,  Keun Hwi CHO ,  Sungmin KIM

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of forming the same are provided. The semiconductor devices may include a substrate, a pair of semiconductor patterns adjacent to each other on the substrate, a gate electrode on the pair of semiconductor patterns, a source/drain pattern connected to the pair of semiconductor patterns, and a ferroelectric pattern on surfaces of the pair of semiconductor patterns. The surfaces of the pair of semiconductor patterns may face each other, and the ferroelectric pattern may define a first space between the pair of semiconductor patterns. The gate electrode may include a work function metal pattern that is in the first space.