-
公开(公告)号:US20240194616A1
公开(公告)日:2024-06-13
申请号:US18514054
申请日:2023-11-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyoungwoo LEE , Anthony Dongick LEE , Kyungmin KIM , Gukhee KIM , Beomjin KIM , Youngwoo KIM , Sangcheol NA , Myeonggyoon CHAE , Seungseok HA
CPC classification number: H01L23/585 , H01L23/481 , H01L23/562
Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.
-
公开(公告)号:US20200267311A1
公开(公告)日:2020-08-20
申请号:US16793242
申请日:2020-02-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Daedong PARK , Beomjin KIM
Abstract: The disclosure provides an electronic apparatus and a controlling method thereof. The electronic apparatus of the disclosure includes a sensor, a camera, and a processor configured to control the electronic apparatus to: obtain information regarding a predetermined object among a plurality of objects included in an imaging region of the camera through the sensor, identify an object region corresponding to the predetermined object from the imaging region of the camera based on the obtained information, and based on the imaging region being captured through the camera, control the camera to not capture the object region.
-
公开(公告)号:US20240258388A1
公开(公告)日:2024-08-01
申请号:US18537546
申请日:2023-12-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyoungwoo LEE , Kyungmin KIM , Gukhee KIM , Beomjin KIM , Youngwoo KIM , Sangcheol NA , Anthony Dongick LEE , Minseung LEE , Myeonggyoon CHAE , Seungseok HA
IPC: H01L29/417 , H01L23/528 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
CPC classification number: H01L29/4175 , H01L23/5286 , H01L27/088 , H01L29/0673 , H01L29/41775 , H01L29/42392 , H01L29/775 , H01L29/78696
Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.
-
公开(公告)号:US20250098264A1
公开(公告)日:2025-03-20
申请号:US18604031
申请日:2024-03-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sangcheol NA , Beomjin KIM , Yoolim AHN , Kyoungwoo LEE , Minseung LEE , Hyeryeong LEE , Keun Hwi CHO , Seungseok HA
IPC: H01L29/417 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: A semiconductor device includes an insulating layer including a first surface, a second surface, and an element isolation trench, an insulating pattern on the first surface of the insulating layer, an active pattern on the insulating pattern and including channel patterns, a source/drain pattern on at least one side of the active pattern, a lower wiring structure on the second surface of the insulating layer, and a through-via that extending in the insulating layer and connecting the source/drain pattern and the lower wiring structure, where the insulating pattern may include a first portion between the insulating layer and the active pattern, a second portion surrounding at least a portion of the through-via, and a third portion on a bottom surface of the element isolation trench.
-
公开(公告)号:US20200264924A1
公开(公告)日:2020-08-20
申请号:US16794400
申请日:2020-02-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Daedong PARK , Jaeseok KANG , Beomjin KIM
IPC: G06F9/48
Abstract: An electronic device may include a communication interface and a processor configured to receive scheduling information comprising a first task and a second task that are to be sequentially performed in a first electronic device from the first electronic device through the communication interface and monitor whether signals corresponding to each of the first task and the second task are received within a timeout time of each of the first task and the second task, which may be obtained based on the scheduling information, and the processor may further, based on receiving information on a third task after receiving first information corresponding to the first task from the first electronic device, renew a timeout time of the second task and monitor whether second information corresponding to the second task is received within the renewed timeout time.
-
-
-
-