公开(公告)号：US20240194616A1

公开(公告)日：2024-06-13

申请号：US18514054

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Anthony Dongick LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L23/58 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L23/585 ,  H01L23/481 ,  H01L23/562

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface facing the first surface and including, in a plan view, a main chip region and a sealing region surrounding the main chip region, a front wiring layer on the first surface of the semiconductor substrate and including a front wiring structure, a back wiring layer on the second surface of the semiconductor substrate and including a power wiring structure, a front ring structure in the front wiring layer of the sealing region, and a back ring structure in the back wiring layer of the sealing region.

公开(公告)号：US20240258388A1

公开(公告)日：2024-08-01

申请号：US18537546

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungwoo LEE ,  Kyungmin KIM ,  Gukhee KIM ,  Beomjin KIM ,  Youngwoo KIM ,  Sangcheol NA ,  Anthony Dongick LEE ,  Minseung LEE ,  Myeonggyoon CHAE ,  Seungseok HA

IPC: H01L29/417 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/4175 ,  H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a source/drain pattern on the active pattern, a first metal layer on the source/drain pattern, the first metal layer comprising a power interconnection line, a through-via electrically connected to the power interconnection line, the through-via vertically extending to penetrate the substrate, a power delivery network layer on a bottom surface of the substrate, and a lower through-via between the power delivery network layer and the through-via. The through-via includes a first metal pattern connected to the lower through-via, and a second metal pattern stacked on the first metal pattern. A density of the first metal pattern is greater than a density of the second metal pattern. A resistivity of the first metal pattern is greater than a resistivity of the second metal pattern.