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    Integrated circuit device
    1.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US12114475B2

    公开(公告)日：2024-10-08

    申请号：US17667195

    申请日：2022-02-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Huijung Kim ,  Myeongdong Lee ,  Inwoo Kim ,  Sunghee Han

    IPC: H01L23/528 ,  H10B12/00 ,  H01L23/522

    CPC classification number: H10B12/0335 ,  H01L23/528 ,  H10B12/315 ,  H10B12/482 ,  H01L23/5226

    Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

    Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device
    2.
    发明授权
    Semiconductor device including storage node electrode including step and method of manufacturing the semiconductor device 有权

    公开(公告)号：US11610891B2

    公开(公告)日：2023-03-21

    申请号：US17725806

    申请日：2022-04-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehwan Cho ,  Junghwan Oh ,  Sangho Lee ,  Junwon Lee ,  Jinwoo Bae ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

    SEMICONDUCTOR MEMORY DEVICES
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20220278121A1

    公开(公告)日：2022-09-01

    申请号：US17748261

    申请日：2022-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

    IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524

    Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210313329A1

    公开(公告)日：2021-10-07

    申请号：US17353398

    申请日：2021-06-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Il Han ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: A semiconductor memory device is provided. The device includes a substrate including a cell region and a peripheral region; a plurality of lower electrodes disposed on the substrate in the cell region; a dielectric layer disposed on the plurality of lower electrodes; a metal containing layer disposed on the dielectric layer; a silicon germanium layer disposed on and electrically connected to the metal containing layer; a conductive pad disposed on and electrically connected to the silicon germanium layer; and an upper electrode contact plug disposed on and electrically connected to the conductive pad; The conductive pad extends from the upper electrode contact plug towards the peripheral region in a first direction, and the silicon germanium layer includes an edge portion that extends past the conductive pad in the first direction.

    SEMICONDUCTOR MEMORY DEVICES
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190206869A1

    公开(公告)日：2019-07-04

    申请号：US16115693

    申请日：2018-08-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Junsoo Kim ,  Sunghee Han ,  Bong-Soo Kim ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L29/10 ,  H01L23/528 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate and a stack including a plurality of layers on the substrate. Each of the plurality of layers includes semiconductor patterns and a first conductive line that is connected to at least one of the semiconductor patterns. A second conductive line and a third conductive line penetrate the stack. The semiconductor patterns include a first semiconductor pattern and a second semiconductor pattern that are adjacent and spaced apart from each other in a first layer among the plurality of layers. The third conductive line is between, and connected in common to, the first and second semiconductor patterns.

    Integrated circuit devices having buried word lines therein
    7.
    发明授权
    Integrated circuit devices having buried word lines therein 有权

    公开(公告)号：US11889681B2

    公开(公告)日：2024-01-30

    申请号：US17720664

    申请日：2022-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

    Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

    SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME
    10.
    发明申请
    SEMICONDUCTOR AND MANUFACTURING METHOD OF THE SAME 有权

    公开(公告)号：US20210066305A1

    公开(公告)日：2021-03-04

    申请号：US16896470

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

    IPC: H01L27/108 ,  H01L23/528

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

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