公开(公告)号：US20240355362A1

公开(公告)日：2024-10-24

申请号：US18503222

申请日：2023-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han Seong Shin ,  Ki Seok Lee ,  Keun Nam Kim ,  Hui-Jung Kim ,  Chan-Sic Yoon

IPC: G11C5/06 ,  H10B12/00

CPC classification number: G11C5/063 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor memory device includes a substrate comprising an element isolation layer, a bit line that extends on the substrate in a first direction, a cell buffer insulating layer between the bit line and the substrate and comprising an upper cell buffer insulating layer and a lower cell buffer insulating layer, a lower storage contact disposed on a plurality of sides of the bit line and comprising a semiconductor epitaxial pattern, a storage pad on the lower storage contact and connected to the lower storage contact and an information storage unit on the storage pad and connected to the storage pad, wherein the upper cell buffer insulating layer is between the lower cell buffer insulating layer and the bit line, and each of the lower cell buffer insulating layer and the upper cell buffer insulating layer comprises an upper surface and a lower surface that are opposite to each other.

公开(公告)号：US20240349491A1

公开(公告)日：2024-10-17

申请号：US18534400

申请日：2023-12-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-Dong Lee ,  Jongmin Kim ,  Taejin Park ,  Seung-Bo Ko ,  Hui-Jung Kim

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

Abstract: An example semiconductor memory device includes first and second active patterns, which are extended in a first direction and are disposed side by side in a second direction. Each of the first and second active patterns includes first and second edge portions, which are spaced apart from each other in the first direction. A pair of word lines are disposed to cross each of the first and second active patterns, a pair of bit lines are disposed on each of the first and second active patterns and are extended in a third direction, and a storage node contacts on the first edge portion of the first active pattern. When measured in the second direction, a first width of the storage node contact at a first level is larger than a second width at a second level. The first level is lower than the second level.

公开(公告)号：US10910382B2

公开(公告)日：2021-02-02

申请号：US16661234

申请日：2019-10-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Keun Nam Kim ,  Yoo Sang Hwang

IPC: H01L27/108 ,  H01L49/02 ,  H01L23/522 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device includes stacking a first mold layer and a first supporter layer, forming a first supporter pattern by etching the first supporter layer to expose the first mold layer, forming an insulating layer to cover the exposed first mold layer and the first supporter pattern, stacking a second mold layer and a second supporter layer on the insulating layer, forming a contact hole by dry-etching the second supporter layer, the second mold layer, the insulating layer, the first supporter pattern, and the first mold layer, forming a lower electrode within the contact hole, removing the first mold layer, the second mold layer, and the insulating layer, and forming an upper electrode on the lower electrode and the first supporter pattern, wherein, during the dry-etching, dry etching rates of the first supporter pattern and the insulating layer are the same.

公开(公告)号：US12052855B2

公开(公告)日：2024-07-30

申请号：US18165692

申请日：2023-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/30 ,  G11C5/063

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US11903184B2

公开(公告)日：2024-02-13

申请号：US17392488

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Il Gweon Kim ,  Hui-Jung Kim ,  Min Hee Cho ,  Jae Ho Hong

IPC: H01L27/108 ,  H01L29/24 ,  H10B12/00 ,  G11C11/402

CPC classification number: H10B12/34 ,  G11C11/4023 ,  H01L29/24

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

公开(公告)号：US11587929B2

公开(公告)日：2023-02-21

申请号：US16880230

申请日：2020-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung Kim ,  Taehyun An ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

IPC: H01L27/108 ,  G11C5/06

Abstract: A semiconductor memory device includes a stack including a plurality of layers vertically stacked on a substrate, each of the layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction crossing the first direction, a gate electrode along each of the semiconductor patterns stacked, a vertical insulating layer on the gate electrode, a stopper layer, and a data storing element electrically connected to each of the semiconductor patterns. The data storing element includes a first electrode electrically connected to each of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes. The stopper layer is between the vertical insulating layer and the second electrode.

公开(公告)号：US11569239B2

公开(公告)日：2023-01-31

申请号：US17126195

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Bong-Soo Kim ,  Jiyoung Kim ,  Hui-Jung Kim ,  Seokhan Park ,  Hunkook Lee ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10 ,  H01L23/522 ,  H01L49/02

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US11502084B2

公开(公告)日：2022-11-15

申请号：US16986367

申请日：2020-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joongchan Shin ,  Changkyu Kim ,  Hui-Jung Kim ,  Iljae Shin ,  Taehyun An ,  Kiseok Lee ,  Eunju Cho ,  Hyungeun Choi ,  Sung-Min Park ,  Ahram Lee ,  Sangyeon Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/822

Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.

公开(公告)号：US20220199625A1

公开(公告)日：2022-06-23

申请号：US17392488

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Hwan Lee ,  Yong Seok Kim ,  Il Gweon Kim ,  Hui-Jung Kim ,  Min Hee Cho ,  Jae Ho Hong

IPC: H01L27/108 ,  G11C11/402 ,  H01L29/24

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

公开(公告)号：US10468350B2

公开(公告)日：2019-11-05

申请号：US15592860

申请日：2017-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunjung Kim ,  Hui-Jung Kim ,  Keunnam Kim ,  Daeik Kim ,  Bong-soo Kim ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L21/764 ,  H01L23/522 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.