公开(公告)号：US10133692B2

公开(公告)日：2018-11-20

申请号：US15190629

申请日：2016-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho Huh ,  Horang Jang ,  Tomas Scherrer ,  Jaewon Lee

IPC: G06F13/16 ,  G06F13/36 ,  G06F13/42 ,  G11C8/10 ,  G11C7/10 ,  G11C7/22

Abstract: A system including: a master device configured to generate a first signal having a periodic pulse, wherein the first signal includes data; and a slave device including a pin, a delay circuit, a buffer, and a processing circuit, wherein the slave device receives the first signal at the pin, delays the first signal with the delay circuit to generate a second signal having a first delay, delays the first signal with the buffer to generate a third signal having a second delay, and reads the data from the second signal using the third signal at the processing circuit.

公开(公告)号：US09755821B2

公开(公告)日：2017-09-05

申请号：US15072470

申请日：2016-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Rang Jang ,  Suh Ho Lee ,  Tomas Scherrer ,  Jun Ho Huh ,  Chul Jin Kim

IPC: H04L7/00 ,  H04L7/04 ,  H04B1/16 ,  G06F13/42 ,  H04L7/033

CPC classification number: H04L7/048 ,  G06F13/4291 ,  H04B1/16 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0054 ,  H04L7/0087 ,  H04L7/0337 ,  H04L7/044

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

公开(公告)号：US20180013546A1

公开(公告)日：2018-01-11

申请号：US15677202

申请日：2017-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho Rang Jang ,  Suh Ho Lee ,  Tomas Scherrer ,  Jun Ho Huh ,  Chul Jin Kim

IPC: H04L7/04 ,  G06F13/42 ,  H04L7/00 ,  H04B1/16 ,  H04L7/033

CPC classification number: H04L7/048 ,  G06F13/4291 ,  H04B1/16 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0054 ,  H04L7/0087 ,  H04L7/0337 ,  H04L7/044

Abstract: A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.