公开(公告)号：US20210057538A1

公开(公告)日：2021-02-25

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Hyunjoon ROH ,  Heungsik PARK ,  Sughyun SUNG ,  Dohaing LEE ,  Wonhyuk LEE

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20190333823A1

公开(公告)日：2019-10-31

申请号：US16503728

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L21/762

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20220122891A1

公开(公告)日：2022-04-21

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20170200651A1

公开(公告)日：2017-07-13

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk LEE ,  JEONGYUN LEE ,  Yongseok LEE ,  Bosoon KIM ,  SANGDUK PARK ,  Seungchul OH ,  YOUNGMOOK OH

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US20220376080A1

公开(公告)日：2022-11-24

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Hyunjoon ROH ,  Heungsik PARK ,  Sughyun SUNG ,  Dohaing LEE ,  Wonhyuk LEE

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20220189870A1

公开(公告)日：2022-06-16

申请号：US17373900

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Dong Kwon KIM ,  Jinwook LEE ,  Jongchul PARK ,  Wonhyuk LEE

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.