公开(公告)号：US20170236921A1

公开(公告)日：2017-08-17

申请号：US15390754

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungseok MIN ,  Seongjin NAM ,  Sughyun SUNG ,  Youngmook OH ,  Migyeong GWON ,  Hyungdong KIM ,  InWon PARK ,  Hyunggoo LEE

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/06 ,  H01L23/535 ,  H01L29/08 ,  H01L21/683 ,  H01L29/161 ,  H01L29/165 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/6833 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device includes a fin structure which vertically protrudes from a substrate and extends in a first direction parallel to a top surface of the substrate. The fin structure includes a lower pattern and an active pattern vertically protruding from a top surface of the lower pattern. The top surface of the lower pattern includes a flat portion substantially parallel to the top surface of the substrate. The lower pattern includes a first sidewall extending in the first direction and a second sidewall extending in a second direction crossing the first direction. The first sidewall is inclined relative to the top surface of the substrate at a first angle greater than a second angle corresponding to the second sidewall that is inclined relative to the top surface of the substrate.

公开(公告)号：US20210057538A1

公开(公告)日：2021-02-25

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Hyunjoon ROH ,  Heungsik PARK ,  Sughyun SUNG ,  Dohaing LEE ,  Wonhyuk LEE

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20240128335A1

公开(公告)日：2024-04-18

申请号：US18369236

申请日：2023-09-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Junki PARK ,  Sunghwan KIM ,  Wandon KIM ,  Sughyun SUNG ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes an active region on a substrate, a plurality of channel layers spaced apart from each other, a gate structure on the substrate, a source/drain region on at least one side of the gate structure, and a contact plug connected to the source/drain region. The contact plug includes a metal-semiconductor compound layer and a barrier layer on the metal-semiconductor compound layer. The contact plug includes a first inclined surface and a second inclined surface positioned where the metal-semiconductor compound layer and the barrier layer directly contact each other. The barrier layer includes first and second ends protruding towards the gate structure. The first and second ends are positioned at a level higher than an upper surface of an uppermost channel layer. An uppermost portion of the metal-semiconductor compound layer is positioned at a level higher than an upper surface of the source/drain region.

公开(公告)号：US20220376080A1

公开(公告)日：2022-11-24

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik SHIN ,  Hyunjoon ROH ,  Heungsik PARK ,  Sughyun SUNG ,  Dohaing LEE ,  Wonhyuk LEE

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US20170133263A1

公开(公告)日：2017-05-11

申请号：US15342456

申请日：2016-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungseok MIN ,  Moojin KIM ,  Seongjin NAM ,  Sughyun SUNG ,  YoungHoon SONG ,  Youngmook OH

IPC: H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01J2237/3347 ,  H01L21/02118 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/10879

Abstract: A method of fabricating a semiconductor device may include forming trenches in a substrate to define a fin structure extending in a direction, forming a device isolation layer to fill the trenches, and removing an upper portion of the device isolation layer to expose an upper side surface of the fin structure. The exposing of the upper side surface of the fin structure may include repeatedly performing an etching cycle including a first step and a second step, and an etching rate of the device isolation layer to the fin structure may be higher in the second step than in the first step.