公开(公告)号：US11133252B2

公开(公告)日：2021-09-28

申请号：US16782307

申请日：2020-02-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Ito ,  Yoshinobu Tanaka ,  Hirofumi Tokita

IPC: H01L23/528 ,  G11C8/14 ,  H01L27/11519 ,  H01L21/02 ,  H01L21/28 ,  H01L21/225 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, such that the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, iteratively performing a first set of non-offset layer patterning processing steps at least twice to form a first part of a terrace region including a set of stepped surfaces which extend in a first horizontal direction, and performing a second set of offset layer patterning processing steps to form a second part of the terrace region and to form a stepped vertical cross-sectional profile for patterned surfaces of the vertically alternating sequence along a second horizontal direction which is perpendicular to the first horizontal direction.

公开(公告)号：US11114459B2

公开(公告)日：2021-09-07

申请号：US16675459

申请日：2019-11-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Hirofumi Tokita ,  Yoshitaka Otsu ,  Fumiaki Toyama ,  Yuki Mizutani

IPC: H01L27/00 ,  H01L29/00 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/28 ,  H01L21/311 ,  H01L29/788

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a substrate, a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, and memory stack structures extending through the alternating stacks in the first or second memory array region. Each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region. Each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region.

公开(公告)号：US11367736B2

公开(公告)日：2022-06-21

申请号：US16881401

申请日：2020-05-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hirofumi Tokita ,  Takayuki Maekura ,  Romain Mentek

IPC: H01L25/065 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11524

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Contact via structures are formed through the vertically alternating stack or the dielectric pillar structures, through the first retro-stepped dielectric material portion, and directly on a first subset of the electrically conductive layers.

公开(公告)号：US11355506B2

公开(公告)日：2022-06-07

申请号：US16881346

申请日：2020-05-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hirofumi Tokita ,  Takayuki Maekura ,  Romain Mentek

IPC: H01L27/11556 ,  H01L23/528 ,  H01L25/065 ,  H01L23/522 ,  H01L21/822 ,  H01L27/11519 ,  H01L27/11524

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. A vertically alternating stack of insulating plates and dielectric material is formed over the first-tier retro-stepped dielectric material portion. Alternatively, dielectric pillar structures may be formed in lieu of the vertically alternating stack. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Contact via structures are formed through the vertically alternating stack or the dielectric pillar structures, through the first retro-stepped dielectric material portion, and directly on a first subset of the electrically conductive layers.

公开(公告)号：US11342245B2

公开(公告)日：2022-05-24

申请号：US16921146

申请日：2020-07-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hirofumi Tokita

IPC: H01L23/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556

Abstract: A first-tier structure includes a first vertically alternating sequence of first continuous insulating layers and first continuous sacrificial material layers and a first-tier retro-stepped dielectric material portion overlying first stepped surfaces of the first vertically alternating sequence. A second vertically alternating sequence of second continuous insulating layers and second continuous sacrificial material layers is formed over the first-tier structure. Retro-stepped dielectric material portions are formed in each of the first-tier structure and the second-tier structure. After formation of memory stack structures, electrically conductive layers replace portions of the first and second continuous sacrificial material layers. Laterally-isolated contact via structures can be formed through the second-tier structure and a first-tier retro-stepped dielectric material portion on first electrically conductive layers in the first-tier structure. Sacrificial landing pad structures can be employed to enable concurrent formation of contact via cavities through the retro-stepped dielectric material portions.

公开(公告)号：US11139237B2

公开(公告)日：2021-10-05

申请号：US16547971

申请日：2019-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Jee-Yeon Kim ,  Fumiaki Toyama ,  Hirofumi Tokita

IPC: H01L27/115 ,  H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.