公开(公告)号：US20180090248A1

公开(公告)日：2018-03-29

申请号：US15709606

申请日：2017-09-20

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn LIEN ,  Jie-An ZHU ,  Zhi-Xian XU ,  Ting-Yi FANG ,  Hong-Zong XU

IPC: H01C17/06 ,  H01C7/102 ,  H01C7/10 ,  H01C1/14 ,  H01C17/28

CPC classification number: H01C17/06 ,  H01C1/14 ,  H01C7/1006 ,  H01C7/102 ,  H01C7/112 ,  H01C7/18 ,  H01C17/065 ,  H01C17/06546 ,  H01C17/281

Abstract: A process for producing a multilayer varistor (MLV) if remained its size unchanged as prior arts is favorable to outstandingly increase overall current-carrying area and improve the performance of final produced MLV; and the MLV has laminated a lower cap, an inner-electrode stack formed from piling up several inner-electrode gaps (g), and an upper cap into a unity, and at least satisfies the condition that the lower cap and the upper cap has a thickness smaller than a thickness of the inner-electrode gap (g), but equal to or greater than 0.1 times of the thickness of the inner-electrode gap (g).