公开(公告)号：US20160240510A1

公开(公告)日：2016-08-18

申请号：US15018896

申请日：2016-02-09

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn LIEN ,  Xing-Xiang HUANG ,  Hsing-Tsai HUANG ,  Jie-An ZHU ,  Hong-Zong XU ,  Yi-Wei CHEN ,  Jung-Chun CHIANG

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49805 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/29294 ,  H01L2224/29311 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29369 ,  H01L2224/32145 ,  H01L2224/32227 ,  H01L2224/33181 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2225/06551 ,  H01L2924/186 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A surface-mount device (SMD) uses no conventional lead frame and contains a multi-function die module formed from either a single die or two or more dies electrically connected in series, in parallel, or in any combination of series and parallel, to provide such a SMD having one or more different functions including wave filtration, rectification, surge protection, sensing, current limiting, voltage regulation or prevention from voltage backflow, as compared to the prior art, the SMD disclosed is formed from fewer components, is simpler to manufacture and more effectively reduce layout wire length and noise.

Abstract translation: 表面安装器件（SMD）不使用常规的引线框架，并且包含由单个管芯或两个或更多个串联，并联或串联和并联的任何组合电连接的模具形成的多功能模具模块， 与现有技术相比，提供这样的SMD具有一个或多个不同的功能，包括波滤波，整流，浪涌保护，感测，限流，电压调节或防止电压回流，所公开的SMD由较少的部件形成，更简单 制造更有效地减少布线长度和噪声。

公开(公告)号：US20180090248A1

公开(公告)日：2018-03-29

申请号：US15709606

申请日：2017-09-20

Applicant: SFI Electronics Technology Inc.

Inventor： Ching-Hohn LIEN ,  Jie-An ZHU ,  Zhi-Xian XU ,  Ting-Yi FANG ,  Hong-Zong XU

IPC: H01C17/06 ,  H01C7/102 ,  H01C7/10 ,  H01C1/14 ,  H01C17/28

CPC classification number: H01C17/06 ,  H01C1/14 ,  H01C7/1006 ,  H01C7/102 ,  H01C7/112 ,  H01C7/18 ,  H01C17/065 ,  H01C17/06546 ,  H01C17/281

Abstract: A process for producing a multilayer varistor (MLV) if remained its size unchanged as prior arts is favorable to outstandingly increase overall current-carrying area and improve the performance of final produced MLV; and the MLV has laminated a lower cap, an inner-electrode stack formed from piling up several inner-electrode gaps (g), and an upper cap into a unity, and at least satisfies the condition that the lower cap and the upper cap has a thickness smaller than a thickness of the inner-electrode gap (g), but equal to or greater than 0.1 times of the thickness of the inner-electrode gap (g).