公开(公告)号：US11138120B2

公开(公告)日：2021-10-05

申请号：US16799566

申请日：2020-02-24

Applicant: SK hynix Inc.

Inventor： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung ,  Chan-Jong Woo

IPC: G06F12/08 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/00 ,  G06F12/0875

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

公开(公告)号：US20200081632A1

公开(公告)日：2020-03-12

申请号：US16680017

申请日：2019-11-11

Applicant: SK hynix Inc.

Inventor： Chan-Jong Woo

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.

公开(公告)号：US10474378B2

公开(公告)日：2019-11-12

申请号：US15670087

申请日：2017-08-07

Applicant: SK hynix Inc.

Inventor： Chan-Jong Woo

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.

公开(公告)号：US11709777B2

公开(公告)日：2023-07-25

申请号：US17493313

申请日：2021-10-04

Applicant: SK hynix Inc.

Inventor： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung ,  Chan-Jong Woo

IPC: G06F12/08 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/00 ,  G06F12/0875

CPC classification number: G06F12/0868 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/00 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/214 ,  G06F2212/451 ,  Y02D10/00

Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

公开(公告)号：US11194479B2

公开(公告)日：2021-12-07

申请号：US16680017

申请日：2019-11-11

Applicant: SK hynix Inc.

Inventor： Chan-Jong Woo

IPC: G06F3/06 ,  G06F13/42 ,  G06F13/40

Abstract: A memory system includes a memory controller; a first memory module, the first memory module including first volatile memory devices; a second memory module, the second memory module including nonvolatile memory devices; a data bus for transmitting data between the memory controller and the first memory module and between the memory controller and the second memory module; a first control bus for transmitting first control signals between the memory controller and the first memory module and between the memory controller and the second memory module; a second control bus for transmitting second control signals between the memory controller and the first memory module; and a third control bus for transmitting third control signals between the memory controller and the second memory module, wherein, in a backup operation, the second control bus and the third control bus are electrically coupled.

公开(公告)号：US10146709B2

公开(公告)日：2018-12-04

申请号：US15666739

申请日：2017-08-02

Applicant: SK hynix Inc.

Inventor： Chan-Jong Woo

IPC: G11C7/00 ,  G06F13/16 ,  G11C8/18 ,  G06F13/42 ,  G11C7/22 ,  G11C5/04

Abstract: A method for operating a memory system including a memory controller and a memory module, the method includes: by the memory controller, applying a read command to the memory module; by the memory module, determining whether the memory module is able to transfer the read data to the memory controller during a regulated section; by the memory module, notifying the memory controller by using a data strobe signal that the memory module is not able to transfer the read data to the memory controller during the regulated section; by the memory controller, applying a status check-out command to the memory module in response to the notification for checking out a status of the memory module; and by the memory module, transferring status information of the memory module to the memory controller in response to the status check-out command.