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    Memory system
    1.
    发明授权
    Memory system 有权

    公开(公告)号：US11138120B2

    公开(公告)日：2021-10-05

    申请号：US16799566

    申请日：2020-02-24

    Applicant: SK hynix Inc.

    Inventor： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung ,  Chan-Jong Woo

    IPC: G06F12/08 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/00 ,  G06F12/0875

    Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

    Signal receiver circuit
    4.
    发明授权
    Signal receiver circuit 有权

    公开(公告)号：US10651829B2

    公开(公告)日：2020-05-12

    申请号：US16234970

    申请日：2018-12-28

    Applicant: SK hynix Inc.

    Inventor： Min-Chang Kim

    IPC: H03K3/00 ,  H03K3/356 ,  H03K5/1534 ,  H04L25/02 ,  H03K3/012 ,  H03K5/02 ,  H03K19/0185 ,  H03K17/687 ,  H03K5/00

    Abstract: A signal receiver circuit includes: a negative voltage applier suitable for applying a negative voltage to a common source node in response to a first clock is at a first logic level; a first sampling transistor coupled between the common source node and a first sampling node to sink a current from the first sampling node to the common source node in response to a first input signal; a second sampling transistor coupled between the common source node and a second sampling node to sink a current from the second sampling node to the common source node in response to a second input signal; an equalizer suitable for equalizing the first sampling node and the second sampling node in response to the first clock is at a second logic level; a precharger suitable for precharging a first output node and a second output node with a pull-up voltage in response to a second clock is at the first logic level, and electrically coupling the first output node and second output node to the second sampling node and the first sampling node, respectively, in response to the second clock is at the second logic level; and an amplifier suitable for amplifying a voltage difference between the first output node and the second output node in response to the second clock is at the second logic level.

    Memory system
    5.
    发明授权
    Memory system 有权

    公开(公告)号：US10466909B2

    公开(公告)日：2019-11-05

    申请号：US15294320

    申请日：2016-10-14

    Applicant: SK hynix Inc.

    Inventor： Chang-Hyun Kim ,  Min-Chang Kim ,  Do-Yun Lee ,  Yong-Woo Lee ,  Jae-Jin Lee ,  Hun-Sam Jung

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data storage memory through the first and second memory devices.

    Signal receiver circuit and method for adjusting weight of compensator
    9.
    发明授权
    Signal receiver circuit and method for adjusting weight of compensator 有权

    公开(公告)号：US10305705B2

    公开(公告)日：2019-05-28

    申请号：US15845318

    申请日：2017-12-18

    Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

    Inventor： Suhwan Kim ,  Min-Chang Kim ,  Deog-Kyoon Jeong

    IPC: H04L25/03 ,  H04B1/12 ,  H04L25/02

    Abstract: A signal receiver circuit may include: a receiver suitable for generating a received signal based on comparison of an input signal with a reference voltage during a normal operation and based on comparison of the input signal with a target voltage during a training operation; a compensator suitable for applying a weight to the received signal to compensate for the input signal; and a weight adjuster suitable for adjusting the weight based on a level of the received signal during the training operation, wherein during the training operation, the input signal toggles between first and second levels, and the receiver is enabled when the input signal is at the first level.

    Heterogeneous package in DIMM
    10.
    发明授权
    Heterogeneous package in DIMM 有权

    公开(公告)号：US10169242B2

    公开(公告)日：2019-01-01

    申请号：US15294387

    申请日：2016-10-14

    Applicant: SK hynix Inc.

    Inventor： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung

    IPC: G06F12/08 ,  G06F12/0875 ,  G06F13/00

    Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

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