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    Memory system
    1.
    发明授权
    Memory system 有权

    公开(公告)号：US11138120B2

    公开(公告)日：2021-10-05

    申请号：US16799566

    申请日：2020-02-24

    申请人： SK hynix Inc.

    发明人： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung ,  Chan-Jong Woo

    IPC分类号： G06F12/08 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/00 ,  G06F12/0875

    摘要： A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

    Latch circuit and latch circuit array including the same
    4.
    发明授权
    Latch circuit and latch circuit array including the same 有权
    锁存电路和锁存电路阵列包括相同的

    公开(公告)号：US09406356B2

    公开(公告)日：2016-08-02

    申请号：US14680852

    申请日：2015-04-07

    申请人： SK hynix Inc.

    发明人： Chang-Hyun Kim ,  Hyun-Gyu Lee

    IPC分类号： G11C7/10

    CPC分类号： G11C7/10 ,  G11C7/02 ,  G11C7/1048 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/4125

    摘要： A latch circuit may include first to fourth storage nodes; first to fourth transistor pairs, each including a PMOS transistor and an NMOS transistor connected in series through a corresponding one of the first to fourth storage nodes, wherein each of the first to fourth storage nodes is connected to a gate of an NMOS transistor of a transistor pair in a previous stage and a gate of a PMOS transistor of a transistor pair in a next stage; a first connection unit suitable for connecting a data bus with a Kth storage node of the first to fourth storage nodes when read and write operations are performed, wherein K is an integer from 1 to 4; and second connection units suitable for connecting the data bus with one or more of the first to fourth storage nodes, except for the Kth storage node, when the write operation is performed.

    摘要翻译： 锁存电路可以包括第一至第四存储节点; 第一至第四晶体管对，每个包括通过第一至第四存储节点中的相应一个串联连接的PMOS晶体管和NMOS晶体管，其中第一至第四存储节点中的每一个连接到NMOS晶体管的栅极 上一级的晶体管对和下一级的晶体管对的PMOS晶体管的栅极; 执行读写操作时适于连接数据总线与第一至第四存储节点的第K个存储节点的第一连接单元，其中K是从1到4的整数; 以及第二连接单元，适于在执行写入操作时将数据总线与除第K个存储节点之外的第一至第四存储节点中的一个或多个相连接。

    Heterogeneous package in DIMM
    6.
    发明授权
    Heterogeneous package in DIMM 有权

    公开(公告)号：US10169242B2

    公开(公告)日：2019-01-01

    申请号：US15294387

    申请日：2016-10-14

    申请人： SK hynix Inc.

    发明人： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung

    IPC分类号： G06F12/08 ,  G06F12/0875 ,  G06F13/00

    摘要： A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

    Address detection circuit, memory system including the same
    10.
    发明授权
    Address detection circuit, memory system including the same 有权

    公开(公告)号：US09646673B2

    公开(公告)日：2017-05-09

    申请号：US14085531

    申请日：2013-11-20

    申请人： SK hynix Inc.

    发明人： Chang-Hyun Kim ,  Choung-Ki Song

    IPC分类号： G11C8/00 ,  G11C11/408 ,  G11C11/406

    CPC分类号： G11C11/408 ,  G11C11/406

    摘要： An address detection circuit includes an address storage unit suitable for receiving an address when an active command is activated, and storing recently inputted N number of addresses; and an address determination unit suitable for determining whether an address currently inputted to the address storage unit is already inputted at least a threshold number of times in each period that the active command is activated M (1≦M≦N) number of times, based on the N number of addresses stored in the address storage unit.