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    Memory system
    1.
    发明授权
    Memory system 有权

    公开(公告)号：US11138120B2

    公开(公告)日：2021-10-05

    申请号：US16799566

    申请日：2020-02-24

    Applicant: SK hynix Inc.

    Inventor： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung ,  Chan-Jong Woo

    IPC: G06F12/08 ,  G06F12/0868 ,  G06F12/0893 ,  G06F13/00 ,  G06F12/0875

    Abstract: A memory system includes: a first memory module including first volatile memories; a second memory module including second volatile memories, non-volatile memories and a module controller; a memory controller controlling the first and second memory modules through second and third control buses, respectively; and a switch array electrically coupling the second and third control buses, wherein the module controller controls the switch array to electrically couple the second and third control buses in a backup operation for backing up data of the first volatile memories to the non-volatile memories, wherein the first and second memory modules include one or more first memory stacks and one or more second memory stacks, respectively, wherein the first volatile memories are stacked in the first memory stacks, and wherein the second volatile memories, the non-volatile memories and the module controller are stacked in the second memory stacks.

    Memory system
    4.
    发明授权
    Memory system 有权

    公开(公告)号：US10466909B2

    公开(公告)日：2019-11-05

    申请号：US15294320

    申请日：2016-10-14

    Applicant: SK hynix Inc.

    Inventor： Chang-Hyun Kim ,  Min-Chang Kim ,  Do-Yun Lee ,  Yong-Woo Lee ,  Jae-Jin Lee ,  Hun-Sam Jung

    IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access data storage memory through the first and second memory devices.

    Majority determination circuit, majority determination method, and semiconductor device
    6.
    发明授权
    Majority determination circuit, majority determination method, and semiconductor device 有权
    多数确定电路，多数确定方法和半导体器件

    公开(公告)号：US09203389B2

    公开(公告)日：2015-12-01

    申请号：US14106825

    申请日：2013-12-15

    Applicant: SK hynix Inc.

    Inventor： Yong-Woo Lee

    IPC: G06F11/08 ,  H03K5/19

    CPC classification number: H03K5/19

    Abstract: A majority determination circuit includes a first determination unit suitable for determining a first majority between bits of a first logic value and a second logic value in a first odd-bit data, wherein the first odd-bit data is an even-bit data with absence of first bit, a second determination unit suitable for determining a second majority between bits of the first logic value and the second logic value in a second odd-bit data, wherein the second odd-bit data is the even-bit data with absence of second bit, and a result combination unit suitable for determining a third majority between bits of the first logic value and the second logic value in an even-bit data based on the first majority and the second majority.

    Abstract translation: 多数确定电路包括第一确定单元，其适于在第一奇数位数据中确定第一逻辑值和第二逻辑值的位之间的第一多数，其中第一奇数位数据是不存在的偶数位数据 第二确定单元，适于在第二奇数位数据中确定第一逻辑值和第二逻辑值的位之间的第二多数，其中第二奇数位数据是不存在第二奇数位数据的偶数位数据 第二位，以及结果组合单元，其适合于基于第一大多数和第二大多数来确定偶数位数据中的第一逻辑值和第二逻辑值的位之间的第三大部分。

    Heterogeneous package in DIMM
    8.
    发明授权
    Heterogeneous package in DIMM 有权

    公开(公告)号：US10169242B2

    公开(公告)日：2019-01-01

    申请号：US15294387

    申请日：2016-10-14

    Applicant: SK hynix Inc.

    Inventor： Yong-Woo Lee ,  Min-Chang Kim ,  Chang-Hyun Kim ,  Do-Yun Lee ,  Jae-Jin Lee ,  Hun-Sam Jung

    IPC: G06F12/08 ,  G06F12/0875 ,  G06F13/00

    Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

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