公开(公告)号：US20250056858A1

公开(公告)日：2025-02-13

申请号：US18720416

申请日：2022-11-16

Applicant: Soitec ,  Soitec Belgium

Inventor： Christelle Veytizou ,  lonut Radu ,  Joff Derluyn ,  Stefan Degroote

IPC: H01L29/20 ,  H01L21/762 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor structure includes a Silicon-On-Insulator substrate and an epitaxial III-N semiconductor layer stack on top of the Silicon-On-Insulator substrate. The Silicon-On-Insulator substrate has a silicon base layer, an intermediate layer on top of the base layer, and a n-type doped silicon top layer on top of the intermediate layer. The intermediate layer includes a trap-rich layer and a buried insulator on top of a trap-rich layer. The epitaxial III-N semiconductor layer stack, which is on top of the Silicon-On-Insulator substrate, includes a first active III-N layer and a second active III-N layer on top of the first active III-N layer. A two-dimensional Electron Gas is located between the first active III-N layer and the second active III-N layer.

公开(公告)号：US20220301847A1

公开(公告)日：2022-09-22

申请号：US17805206

申请日：2022-06-02

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frédéric Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20210057635A1

公开(公告)日：2021-02-25

申请号：US17044132

申请日：2019-03-13

Applicant: Soitec

Inventor： Frédéric Allibert ,  Christelle Veytizou

IPC: H01L41/08 ,  H01L41/319 ,  H01L41/43 ,  H03H3/10 ,  H03H9/02

Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.

公开(公告)号：US20190058031A1

公开(公告)日：2019-02-21

申请号：US16080279

申请日：2017-02-23

Applicant: Centre National de la Recherche Scientifque ,  Universite Claude Bernard Lyon 1 ,  Soitec

Inventor： Christophe Figuet ,  Oleg Kononchuk ,  Kassam Alassaad ,  Gabriel Ferro ,  Véronique Souliere ,  Christelle Veytizou ,  Taguhi Yeghoyan

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/16 ,  H01L21/02

Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

公开(公告)号：US11974505B2

公开(公告)日：2024-04-30

申请号：US17044132

申请日：2019-03-13

Applicant: Soitec

Inventor： Frédéric Allibert ,  Christelle Veytizou

IPC: H03H9/02 ,  H03H3/10 ,  H10N30/00 ,  H10N30/079 ,  H10N30/097

CPC classification number: H10N30/10516 ,  H03H3/10 ,  H03H9/02559 ,  H03H9/02574 ,  H03H9/02834 ,  H10N30/079 ,  H10N30/097

Abstract: A hybrid structure for a surface acoustic wave device comprises a working layer of piezoelectric material assembled with a support substrate having a lower coefficient of thermal expansion than that of the working layer, and an intermediate layer located between the working layer and the support substrate. The intermediate layer is a sintered composite layer formed from powders of at least a first material and a second material different from the first.

公开(公告)号：US20220359272A1

公开(公告)日：2022-11-10

申请号：US17623499

申请日：2020-03-25

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  Soitec

Inventor： Emmanuel Augendre ,  Frédéric Gaillard ,  Thomas Lorne ,  Emmanuel Rolland ,  Christelle Veytizou ,  Isabelle Bertrand ,  Frédéric Allibert

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor structure for radio frequency applications includes a support substrate made of silicon and comprising a mesoporous layer, a dielectric layer arranged on the mesoporous layer and a superficial layer arranged on the dielectric layer. The mesoporous layer comprises hollow pores, the internal walls of which are mainly lined with oxide. The mesoporous layer has a thickness between 3 and 40 microns and a resistivity greater than 20 kohm.cm over its entire thickness. The support substrate has a resistivity between 0.5 and 4 ohm.cm. The invention also relates to a method for producing such a semiconductor structure.

公开(公告)号：US20220399200A1

公开(公告)日：2022-12-15

申请号：US17755812

申请日：2020-11-25

Applicant: Soitec

Inventor： Young-Pil Kim ,  Isabelle Bertrand ,  Christelle Veytizou

IPC: H01L21/02 ,  H01L41/053 ,  H01L21/762 ,  H01L41/312

Abstract: A method for forming a high resistivity handle substrate for a composite substrate comprises: providing a base substrate made of silicon; exposing the base substrate to a carbon single precursor at a pressure below atmospheric pressure to form a polycrystalline silicon carbide layer having a thickness of at least 10 nm on the surface of the base substrate; and then growing a polycrystalline charge trapping layer on the carbon-containing layer.

公开(公告)号：US11251265B2

公开(公告)日：2022-02-15

申请号：US16080279

申请日：2017-02-23

Applicant: Centre National de la Recherche Scientifique ,  Universite Claude Bernard Lyon 1 ,  Soitec

Inventor： Christophe Figuet ,  Oleg Kononchuk ,  Kassam Alassaad ,  Gabriel Ferro ,  Véronique Souliere ,  Christelle Veytizou ,  Taguhi Yeghoyan

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L29/16

Abstract: A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.

公开(公告)号：US20210183691A1

公开(公告)日：2021-06-17

申请号：US17257176

申请日：2018-07-05

Applicant: Soitec

Inventor： Christelle Veytizou ,  Patrick Reynaud ,  Oleg Kononchuk ,  Frédéric Allibert

IPC: H01L21/762 ,  H01L21/02 ,  H01L23/66 ,  H01L29/16 ,  H01Q1/22

Abstract: A substrate for applications in the fields of radiofrequency electronics and microelectronics, comprises: a base substrate; a single carbon layer positioned on and directly in contact with the base substrate, with the carbon layer having a thickness ranging from 1 nm to 5 nm; an insulator layer positioned on the carbon layer; and a device layer positioned on the insulator layer. The disclosure also relates to a process for manufacturing such a substrate

公开(公告)号：US20210028057A1

公开(公告)日：2021-01-28

申请号：US16982986

申请日：2019-03-13

Applicant: Soitec

Inventor： Frederic Allibert ,  Christelle Veytizou ,  Damien Radisson

IPC: H01L21/762 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373

Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.