公开(公告)号：US11688627B2

公开(公告)日：2023-06-27

申请号：US16982986

申请日：2019-03-13

Applicant: Soitec

Inventor： Frederic Allibert ,  Christelle Veytizou ,  Damien Radisson

IPC: H01L21/762 ,  H01L23/29 ,  H01L23/31 ,  H01L23/373

CPC classification number: H01L21/76251 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3733

Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.

公开(公告)号：US11373856B2

公开(公告)日：2022-06-28

申请号：US16476415

申请日：2018-01-11

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20200020520A1

公开(公告)日：2020-01-16

申请号：US16476415

申请日：2018-01-11

Applicant: Soitec

Inventor： Patrick Reynaud ,  Marcel Broekaart ,  Frederic Allibert ,  Christelle Veytizou ,  Luciana Capello ,  Isabelle Bertrand

IPC: H01L21/02 ,  H01L21/762

Abstract: A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm·cm and a thickness greater than 5 microns positioned on the first insulating layer.

公开(公告)号：US20210028057A1

公开(公告)日：2021-01-28

申请号：US16982986

申请日：2019-03-13

Applicant: Soitec

Inventor： Frederic Allibert ,  Christelle Veytizou ,  Damien Radisson

IPC: H01L21/762 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373

Abstract: A substrate for radiofrequency microelectronic devices comprises a carrier substrate made of a semi-conductor, a sintered composite layer disposed on the carrier substrate and formed from powders of at least a first dielectric material and a second dielectric different from the first material, the sintered composite layer having a thickness larger than 5 microns and a thermal expansion coefficient that is matched with that of the carrier substrate to plus or minus 30%.

公开(公告)号：US20140015023A1

公开(公告)日：2014-01-16

申请号：US14027528

申请日：2013-09-16

Applicant: Soitec

Inventor： Frederic Allibert ,  Gweltaz Gaudin ,  Fabrice Lallement ,  Didier Landru ,  Karine Landry ,  Carlos Mazure ,  Mohamad A. Shaheen

IPC: H01L31/0248

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.

Abstract translation: 本发明的实施例涉及包括基底晶片，绝缘层和顶部半导体层的基板，其中绝缘层至少包括电荷密度高于1010电荷/ cm 2的绝对值的区域。 本发明还涉及制造这种基材的方法。

公开(公告)号：US20130134547A1

公开(公告)日：2013-05-30

申请号：US13748146

申请日：2013-01-23

Applicant: Soitec ,  Commissariat à I'Énergie Atomique

Inventor： Thomas Signamarcheix ,  Frederic Allibert ,  Chrystel Deguet

IPC: H01L29/16

CPC classification number: H01L29/16 ,  H01L21/318 ,  H01L21/76254 ,  H01L21/76283

Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.

Abstract translation: 本发明涉及一种用于制造局部钝化的绝缘体上的锗衬底的方法，其中为了获得良好的电子迁移率，在局部位置提供氮化区域。 使用等离子体处理实现氮化。 所得到的基底也构成本发明的一部分。

公开(公告)号：US20200169222A1

公开(公告)日：2020-05-28

申请号：US16614732

申请日：2018-05-23

Applicant: Soitec

Inventor： Marcel Broekaart ,  Frederic Allibert ,  Eric Desbonnets ,  Jean-Pierre Raskin ,  Martin Rack

IPC: H03C7/00 ,  H01L23/66

Abstract: A method for minimizing harmonic distortion and/or intermodulation distortion of a radiofrequency signal propagating in a radiofrequency circuit formed on a semiconductor substrate coated with an electrically insulating layer, wherein a curve representing the distortion as a function of a power of the input or output signal exhibits a trough around a given power (PDip), the method comprises applying, between the radiofrequency circuit and the semiconductor substrate, an electrical potential difference (VGB) chosen so as to move the trough toward a given operating power of the radiofrequency circuit.

公开(公告)号：US20150168326A1

公开(公告)日：2015-06-18

申请号：US14372192

申请日：2013-01-15

Applicant: Soitec

Inventor： Frederic Allibert

IPC: G01N27/04

CPC classification number: G01N27/041 ,  G01R31/2831

Abstract: The invention relates to a method for testing a semiconductor substrate (1) for radiofrequency applications, characterized in that the electrical resistivity profile of the substrate as a function of depth, is measured and, using the profile, a criterion is calculated, defined by the formula (I): where D is the integration depth, σ(x) is the electrical conductivity measured at a depth x in the substrate, and L is a characteristic attenuation length of the electric field in the substrate. The invention also relates to a method for selecting a semiconductor substrate (1) for radiofrequency applications and to a device for implementing these methods.

Abstract translation: 本发明涉及一种用于测试射频应用的半导体衬底（1）的方法，其特征在于测量作为深度的函数的衬底的电阻率分布，并且使用该简档来计算标准，由 公式（I）：其中D是积分深度，＆sgr;（x）是在衬底中在深度x测量的电导率，L是衬底中电场的特征衰减长度。 本发明还涉及用于选择用于射频应用的半导体衬底（1）和用于实现这些方法的装置的方法。

公开(公告)号：US20190259617A1

公开(公告)日：2019-08-22

申请号：US16342133

申请日：2017-09-29

Applicant: Soitec

Inventor： Frederic Allibert

IPC: H01L21/225 ,  H01L21/762

Abstract: A method for dissolving a buried oxide in a silicon-on-insulator wafer comprises providing a silicon-on-insulator wafer having a silicon layer attached to a carrier substrate via a buried oxide layer, and annealing the silicon-on-insulator wafer to at least partially dissolve the buried oxide layer. The method further comprises a step of providing an oxygen scavenging layer on or over the silicon layer before the annealing step.

公开(公告)号：US20160372484A1

公开(公告)日：2016-12-22

申请号：US15176925

申请日：2016-06-08

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Frederic Allibert ,  Christophe Maleville

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

Abstract: A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency, RF, circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

Abstract translation: 一种用于制造绝缘体上绝缘体上的高电阻半导体衬底的方法，包括以下步骤：a）在高电阻率衬底上形成电介质层和半导体层，使得电介质层布置在高电阻率衬底和 半导体层; b）在所述半导体层上形成硬掩模或抗蚀剂，其中所述硬掩模或抗蚀剂在预定位置具有至少一个开口; c）通过所述硬掩模或抗蚀剂，所述半导体层和所述电介质层的所述至少一个开口离子注入杂质元素，在所述高电阻率衬底中形成至少一个掺杂区域; d）去除硬掩模或抗蚀剂; 以及e）在所述半导体层中和/或之上形成至少部分地与所述高电阻率衬底中的所述至少一个掺杂区域重叠的射频RF电路。