公开(公告)号：US20210118429A1

公开(公告)日：2021-04-22

申请号：US17112287

申请日：2020-12-04

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN

IPC: G10L15/08 ,  G10L15/02 ,  G10L15/16

Abstract: It discloses a speech feature reuse-based storing and calculating compression method for a keyword-spotting CNN, and belongs to the technical filed of calculating, reckoning or counting. If the updated row number of input data is equal to a convolution step size, every time new input data arrive, an input layer of a neural network replaces the earliest part of the input data with the new input data and meanwhile adjusts an addressing sequence of the input data, thereby performing an operation on the input data and corresponding convolution kernels in an arrival sequence of the input data, and an operation result is stored in an intermediate data memory of the neural network to update corresponding data.

公开(公告)号：US20180253521A1

公开(公告)日：2018-09-06

申请号：US15560161

申请日：2017-02-24

Applicant: Southeast University

Inventor： Weiwei SHAN ,  Wentao DAI ,  Jun YANG ,  Longxing SHI

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5031 ,  G06F2217/84 ,  H03K5/1534 ,  H03K5/19

Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, the present invention eliminates the need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing the area and the power consumption of the online monitoring unit significantly and improving the energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, the time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by PVT variations, thus enabling the minimization of timing margin and ensuring higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.

公开(公告)号：US20210174184A1

公开(公告)日：2021-06-10

申请号：US17181595

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Ziyu LI ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/04

Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.

公开(公告)号：US20210090553A1

公开(公告)日：2021-03-25

申请号：US17112246

申请日：2020-12-04

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Lixuan ZHU

IPC: G10L15/02 ,  G10L25/45 ,  G10L25/27

Abstract: It discloses a serial FFT-based low-power MFCC speech feature extraction circuit, and belongs to the technical field of calculation, reckoning or counting. The circuit is oriented toward the field of intelligence, and is adapted to a hardware circuit design by optimizing an MFCC algorithm, and a serial FFT algorithm and an approximation operation on a multiplication are fully used, thereby greatly reducing a circuit area and power. The entire circuit includes a preprocessing module, a framing and windowing module, an FFT module, a Mel filtration module, and a logarithm and DCT module. The improved FFT algorithm uses a serial pipeline manner to process data, and a time of an audio frame is effectively utilized, thereby reducing a storage area and operation frequency of the circuit under the condition of meeting an output requirement.

公开(公告)号：US20220189459A1

公开(公告)日：2022-06-16

申请号：US17181908

申请日：2021-02-22

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Lixuan ZHU ,  Jun YANG ,  Longxing SHI

IPC: G10L15/02 ,  G10L25/24 ,  G06F17/14

Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.

公开(公告)号：US20210313975A1

公开(公告)日：2021-10-07

申请号：US16957724

申请日：2019-07-09

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Jun YANG ,  Longxing SHI

IPC: H03K5/14 ,  H03K5/131 ,  G04F10/00

Abstract: A two-way adaptive clock circuit supporting a wide frequency range is composed of a phase clock generating module, a phase clock selecting module, an adaptive clock stretching or compressing amount regulating circuit module and a control module. The adaptive clock stretching or compressing amount regulating circuit module can monitor delay information of a critical path in a chip in real time and feed the information back into the control module. After receiving a clock stretching or compressing enable signal and a stretching or compressing scale signal, the control module selects a target phase clock from clocks generated by the phase clock generating module to rapidly regulate an adaptive clock in a current cycle. The present invention is applied to an adaptive voltage frequency regulating circuit based on on-line time sequence monitoring.

公开(公告)号：US20210312959A1

公开(公告)日：2021-10-07

申请号：US17042921

申请日：2019-10-30

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Tao WANG

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/06 ,  G11C8/08 ,  G06N3/063 ,  H03K3/356 ,  H03K19/21

Abstract: An in-memory computing circuit for a fully connected binary neural network includes an input latch circuit, a counting addressing module, an address selector, a decoding and word line drive circuit, a memory array, a pre-charge circuit, a writing bit line drive circuit, a replica bit line column cell, a timing control circuit, a sensitive amplifier and a NAND gate array, an output latch circuit and an analog delay chain. A parallel XNOR operation is performed in the circuit on the SRAM bit line, and the accumulation operation, activation operation and other operations are performed by the delay chain in the time domain. Partial calculation is completed while reading the data, and the delay chain with a small area occupation can be integrated with SRAM, thus reducing the energy consumption of the memory access process. Multi-column parallel computing also improves system throughput.

公开(公告)号：US20210089874A1

公开(公告)日：2021-03-25

申请号：US17112329

申请日：2020-12-04

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Boyang CHENG ,  Jun YANG ,  Longxing SHI

IPC: G06N3/063 ,  G06N3/04 ,  G06F1/3203

Abstract: It discloses an ultra-low power keyword spotting neural network circuit and a method for mapping data. A neural network model used is a depthwise separable convolutional neural network, of which a weight value and an intermediate activation value are both binarized during training, to obtain a lightweight neural network model with a small memory size and a small computation quantity. The circuit is designed on the basis of a data processing unit array, utilizes a memory module to memorize a weight parameter and intermediate data of a keyword spotting neural network, data control and accuracy configuration of the data processing unit array are completed by means of a control module and a data mapping module, and the data processing unit array performs a neural network computation with hybrid accuracy; and the method for mapping the data configures.

公开(公告)号：US20180191335A1

公开(公告)日：2018-07-05

申请号：US15562893

申请日：2017-02-24

Applicant: Southeast University

Inventor： Weiwei SHAN ,  Liang WAN ,  Longxing SHI

IPC: H03K5/133 ,  H03L7/18

CPC classification number: H03K5/133 ,  H03K5/05 ,  H03L7/18

Abstract: A PVTM-based wide voltage range clock stretching circuit is disclosed. The circuit consists of a PVTM circuit module, a phase clock generation module, a clock synchronization selection module and a control module. The PVTM circuit module monitors in real time the delay information of an on-chip delay unit to monitor the operating environment of the circuit, and feeds the delay information back to the control module. Under the control of a clock stretching enable signal and a clock stretching extent signal, the control module selects a target phase clock from the clocks generated by the phase clock generation module in accordance with the feedback from the PVTM, enabling the stretching of system clock within a single cycle in different PVT conditions. Sophisticated gate devices are not required, and the cost of area and power consumption are kept to minimal.

公开(公告)号：US20150309897A1

公开(公告)日：2015-10-29

申请号：US14442071

申请日：2013-08-30

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weiwei SHAN ,  Chaoxuan TIAN ,  Huafang SUN ,  Longxing SHI

IPC: G06F11/20

CPC classification number: G06F11/2035 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/0721 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/3024 ,  G06F11/3062 ,  G06F11/3093 ,  G06F2201/805 ,  G06F2201/85 ,  Y02D10/126 ,  Y02D10/172

Abstract: Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits (1), an error signal statistics module (2), a voltage frequency control module (3), an error recovery control module (4), an in-situ error recovery module (5) and an upper-layer error recovery module (6), wherein each of the on-chip monitoring circuits (1) is integrated at the end of each stage of assembly lines of the previous N−1 stages of assembly lines of a CPU kernel with an N-stage assembly line structure, so as to monitor the time sequence information about each clock period of an operating circuit, wherein N is a positive integer which is greater than or equal to 3 and less than 20. The present invention provides the on-line time sequence monitoring on the CPU kernel with N stages of assembly lines to search for the lowest possible operating voltage of the circuit, and to reduce the margin of the operating voltage reserved for the circuit in the design stage, thereby significantly reducing the power consumption of the circuit and improving the energy efficiency of the circuit.

Abstract translation: 公开了面向CPU装配线的错误恢复电路，包括：片上监控电路（1），误差信号统计模块（2），电压频率控制模块（3），错误恢复控制模块（4） 原位错误恢复模块（5）和上层错误恢复模块（6），其中片上监控电路（1）中的每一个在前一个N- 1级具有N级组装线结构的CPU内核的组装线，以便监视关于操作电路的每个时钟周期的时间序列信息，其中N是大于或等于3的正整数，以及 小于20.本发明提供了在具有N级装配线的CPU内核上的在线时间序列监视，以搜索电路的最低可能工作电压，并且减小为电路保留的工作电压的余量 在设计阶段，从而得到信誉 显着降低电路的功耗并提高电路的能量效率。