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公开(公告)号：US20210311514A1
公开(公告)日：2021-10-07
申请号：US16966476
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao CHEN , Jun YANG , Xinning LIU
Abstract: A low-temperature drift ultra-low-power linear regulator includes eight PMOS transistors, two resistors, two capacitors and three NMOS transistors. The eight PMOS transistors include PMOS transistor PM1 to PMOS transistor PM8. The two resistors include resistor R1 and resistor R2. The two capacitors include capacitor C1 and capacitor C2. The three NMOS transistors include NMOS transistor NM1, NMOS transistor NM2 and NMOS transistor NM3. From right to left, the linear regulator includes a PTAT voltage core starting circuit, a PTAT voltage core circuit, a negative temperature characteristic generating circuit and a driver stage closed-loop control circuit. PM5-PM8 form a feedback circuit. The feedback circuit clamps the current flowing through PM6 to be proportional to PM2 to obtain a temperature-stable output voltage, and can dynamically adjust the gate voltage of PM5 according to the change of load current to output different currents according to the load demand.
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2.发明申请公开(公告)号：US20210191344A1
公开(公告)日：2021-06-24
申请号：US17253558
申请日：2019-07-08
Applicant: SOUTHEAST UNIVERSITY
Inventor： Jun YANG , Xiangyang LIU , Jianliang MAO , Shihua LI
Abstract: The present invention provides a generalized proportional integral observer-based method for compensating for visual-measurement time lag of an electro-optical tracking system. For visual-measurement time lag present in an electro-optical tracking system, an improved generalized proportional integral observer-based feedback control method is used to mitigate the impact of the measurement time lag on the system and suppress kinematic uncertainty of the system. The core of the method lies in that an observer is used to estimate a state, uncertainty, and a difference of the system at a previous moment, a state and uncertainty of the system at a current moment are then calculated by using these estimated values and a state-space model of the system, and a control input of the system is finally acquired according to the estimated values of the state and uncertainty of the system at the current moment. The method mitigates the adverse impact of visual-measurement time lag on the system and enhances the uncertainty suppression and the tracking precision of the system.
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公开(公告)号：US20210056468A1
公开(公告)日：2021-02-25
申请号：US17043715
申请日：2019-03-12
Applicant: Southeast University
Inventor： Peng CAO , Bingqian XU , Jingjing GUO , Mengxiao LI , Jun YANG
Abstract: A method for predicting the fluctuation of circuit path delay on the basis of machine learning, comprising the following steps: S1: selecting suitable sample characteristics by means of analyzing the relationship between circuit characteristics and path delay; S2: generating a random path by means of enumerating values of randomized parameters, acquiring the maximum path delay by means of performing Monte Carlo simulation on the random path, selecting a reliable path by means of the 3σ standard, and using the sample characteristics and path delay of the reliable path as a sample set (D); S3: establishing a path delay prediction model, and adjusting parameters of the model; S4: verifying the precision and stability of the path delay prediction model; S5: obtaining the path delay. The method for predicting the fluctuation of circuit path delay on the basis of machine learning has the advantages of high precision and low running time, thereby having remarkable advantages in the accuracy and efficiency of timing analysis.
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公开(公告)号：US20200342295A1
公开(公告)日：2020-10-29
申请号：US16757421
申请日：2019-01-24
Applicant: Southeast University
Inventor： Bo LIU , Yu GONG , Wei GE , Jun YANG , Longxing SHI
Abstract: The present invention relates to the field of analog integrated circuits, and provides a multiply-accumulate calculation method and circuit suitable for a neural network, which realizes large-scale multiply-accumulate calculation of the neural network with low power consumption and high speed. The multiply-accumulate calculation circuit comprises a multiplication calculation circuit array and an accumulation calculation circuit. The multiplication calculation circuit array is composed of M groups of multiplication calculation circuits. Each group of multiplication calculation circuits is composed of one multiplication array unit and eight selection-shift units. The order of the multiplication array unit is quantized in real time by using on-chip training to provide a shared input for the selection-shift units, achieving increased operating rate and reduced power consumption. The accumulation calculation circuit is composed of a delay accumulation circuit, a TDC conversion circuit, and a shift-addition circuit in series. The delay accumulation circuit comprises eight controllable delay chains for dynamically controlling the number of iterations and accumulating data multiple times in a time domain, so as to meet the difference in calculation scale of different network layers, save hardware storage space, reduce calculation complexity, and reduce data scheduling.
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公开(公告)号：US20210344266A1
公开(公告)日：2021-11-04
申请号：US16968594
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao CHEN , Jun YANG , Xinning LIU
Abstract: An ultra-low-power mode control circuit for a power converter includes four modules: a level shift circuit, a start circuit, a static clamp circuit, and a control circuit. When a chip is powered on and a core voltage has not been established, the control circuit firstly starts a power source built-in clock to support operation of the power converter. When the core voltage is established, the control circuit determines whether to switch to an external clock according to a level of a mode selection signal. After the core voltage is powered down, the control circuit automatically wakes up the built-in clock to work.
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Patent Agency Ranking
公开(公告)号：US20210174184A1
公开(公告)日：2021-06-10
申请号：US17181595
申请日：2021-02-22
Applicant: SOUTHEAST UNIVERSITY
Inventor： Weiwei SHAN , Ziyu LI , Jun YANG , Longxing SHI
Abstract: The present invention discloses an ultralow-power negative margin timing monitoring method of a neural network circuit, relates to an adaptive voltage regulation technology based on on-chip timing detection, and belongs to the technical field of low-power design of integrated circuit. The present invention provides an ultralow-power operating method of neural network circuit. By inserting a timing monitoring unit in specific position of critical paths and setting partial circuits to operate under “negative margin”, the system can further lower voltage, compress the timing slack, and obtain higher power gain.
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公开(公告)号：US20210351693A1
公开(公告)日：2021-11-11
申请号：US16966474
申请日：2020-04-30
Applicant: SOUTHEAST UNIVERSITY
Inventor： Chao CHEN , Jun YANG , Xinning LIU
IPC: H02M3/07
Abstract: A high energy efficiency switched-capacitor power converter includes the transmission gates T1-T7, the capacitors C1-C4, the load capacitor CL, and resistors, PMOS tubes and NMOS tubes. The power converter converts a stable input voltage of 3V into an output voltage of 1V by means of charge transfer. In the state of timing sequence 1, the on-chip capacitor C1, the capacitor C2 and the load capacitor CL are charged in series. In the state of timing sequence 2, the capacitor C1 and the capacitor C2 are connected in parallel to the capacitor CL to supplement the charge loss due to load for the capacitor CL. When the establishment is completed, the voltages across the capacitor C1, the capacitor C2, and the capacitor CL are basically the same. At this time, the voltage drop across the switch tube approximates 0 V during the charge transfer process.
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8.发明申请公开(公告)号：US20210207546A1
公开(公告)日：2021-07-08
申请号：US16618380
申请日：2018-11-20
Applicant: SOUTHEAST UNIVERSITY
Abstract: A nonlinear disturbance rejection control apparatus and method for electronic throttle control systems are invented to control the electronic throttle system and to achieve a continuous finite-time disturbance rejection control goal. A control sub-apparatus and method are proposed with an observing sub-apparatus and method for controlling the opening angle of an electronic throttle valve. A mathematical model of the electronic throttle system is analyzed and a control-oriented model is presented with the formation of a lumped disturbance. With combination of the continuous terminal sliding mode control method and the output feedback control method, based on the finite-time high-order sliding mode observer, the preferred control performance is guaranteed, where both the dynamic and static performance of the system is effectively improved.
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公开(公告)号：US20180253521A1
公开(公告)日：2018-09-06
申请号：US15560161
申请日：2017-02-24
Applicant: Southeast University
Inventor： Weiwei SHAN , Wentao DAI , Jun YANG , Longxing SHI
IPC: G06F17/50
CPC classification number: G06F17/5045 , G06F17/5031 , G06F2217/84 , H03K5/1534 , H03K5/19
Abstract: An online monitoring unit and a control circuit for ultra-wide voltage range applications are disclosed. Compared with a conventional online monitoring unit, the present invention eliminates the need to reserve delay units, replaces flip-flops in the conventional online monitoring unit with a latch, and uses a transition detector with fewer transistors than that of a shadow latch in the conventional online monitoring unit, thereby reducing the area and the power consumption of the online monitoring unit significantly and improving the energy efficiency of online monitoring techniques. In addition, in the ultra-wide voltage range applications, the time borrowing property of the latch adopted by the present invention can be utilized to prevent a timing error caused by PVT variations, thus enabling the minimization of timing margin and ensuring higher power efficiency. The present invention also discloses a control circuit for use with the online monitoring unit.
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10.发明申请公开(公告)号：US20220189459A1
公开(公告)日：2022-06-16
申请号：US17181908
申请日：2021-02-22
Applicant: SOUTHEAST UNIVERSITY
Inventor： Weiwei SHAN , Lixuan ZHU , Jun YANG , Longxing SHI
Abstract: The present invention discloses an ultra-low-power speech feature extraction circuit based on non-overlapping framing and serial fast Fourier transform (FFT), and belongs to the technical field of computation, calculation or counting. The circuit is oriented to the field of intelligence, and is integrally composed of a pre-process module, a windowing module, a Fourier transform module, a Mel filtering module, an adjacent frame merging module, a discrete cosine transform (DCT) module and other modules by optimizing the architecture of a Mel-frequency Cepstral Coefficients (MFCC) algorithm. Large-scale storage caused by framing is avoided in a non-overlapping framing mode, storage contained in the MFCC algorithm is further reduced, and the circuit area and the power consumption are greatly reduced. An FFT algorithm in the feature extraction circuit adopts a serial pipeline mode to process data, makes full use of the characteristics of serial inflow of audio data, and further reduces the storage area and operations of the circuit.
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