公开(公告)号：US20200098760A1

公开(公告)日：2020-03-26

申请号：US16697103

申请日：2019-11-26

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US20170084733A1

公开(公告)日：2017-03-23

申请号：US15365640

申请日：2016-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US20170047425A1

公开(公告)日：2017-02-16

申请号：US14826803

申请日：2015-08-14

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporations ,  STMicroelectronics, Inc.

Inventor： Steven BENTLEY ,  Jody FRONHEISER ,  Xin MIAO ,  Joseph WASHINGTON ,  Pierre MORIN

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06 ,  H01L21/324

CPC classification number: H01L29/66537 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0638 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165

Abstract: A method of performing an early PTS implant and forming a buffer layer under a bulk or fin channel to control doping in the channel and the resulting bulk or fin device are provided. Embodiments include forming a recess in a substrate; forming a PTS layer below a bottom surface of the recess; forming a buffer layer on the bottom surface and on side surfaces of the recess; forming a channel layer on and adjacent to the buffer layer; and annealing the channel, buffer, and PTS layers.

Abstract translation: 提供了一种执行早期PTS植入和在体或鳍通道下形成缓冲层以控制沟道中的掺杂并且产生的体或鳍器件的方法。 实施例包括在基板中形成凹部; 在所述凹部的底表面下方形成PTS层; 在所述凹部的底表面和侧表面上形成缓冲层; 在缓冲层上和邻近缓冲层上形成沟道层; 并对通道，缓冲器和PTS层进行退火。

公开(公告)号：US20160172497A1

公开(公告)日：2016-06-16

申请号：US14975534

申请日：2015-12-18

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas LOUBET ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US20210050449A1

公开(公告)日：2021-02-18

申请号：US17087218

申请日：2020-11-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US20180158945A1

公开(公告)日：2018-06-07

申请号：US15884843

申请日：2018-01-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/417 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

公开(公告)号：US20170345935A1

公开(公告)日：2017-11-30

申请号：US15677855

申请日：2017-08-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L21/84 ,  H01L29/16 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092 ,  H01L29/786 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78654

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

公开(公告)号：US20160149037A1

公开(公告)日：2016-05-26

申请号：US14950833

申请日：2015-11-24

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMICROELECTRONICS, Inc.

Inventor： Shay REBOH ,  Pierre MORIN

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

Abstract: Method of making at least one transistor strained channel semiconducting structure, comprising steps to form a sacrificial gate block and insulating spacers arranged in contact with the lateral faces of the sacrificial gate block, form sacrificial regions in contact with the lateral faces of said semiconducting zone, said sacrificial regions being configured so as to apply a strain on said semiconducting zone, remove said sacrificial gate block between said insulating spacers, replace said sacrificial gate block by a replacement gate block between said insulating spacers, remove said sacrificial regions, and replace said sacrificial regions by replacement regions in contact with the lateral faces of said semiconducting zone, on a semiconducting zone that will form a transistor channel region.

Abstract translation: 制造至少一个晶体管应变通道半导体结构的方法，包括形成牺牲栅极块的步骤和与牺牲栅极块的侧面接触地布置的绝缘间隔物，形成与所述半导体区域的侧面接触的牺牲区域， 所述牺牲区域被配置为在所述半导体区域上施加应变，去除所述绝缘间隔物之间​​的所述牺牲栅极块，用所述绝缘间隔物之间​​的置换栅极块代替所述牺牲栅极块，去除所述牺牲区域， 区域，其与形成晶体管沟道区域的半导体区域相接触，与所述半导体区域的侧面接触。

公开(公告)号：US20170263495A1

公开(公告)日：2017-09-14

申请号：US15457447

申请日：2017-03-13

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Emmanuel AUGENDRE ,  Nicolas LOUBET ,  Sylvain MAITREJEAN ,  Pierre MORIN

IPC: H01L21/762 ,  H01L29/16 ,  H01L29/78

Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.

公开(公告)号：US20160307899A1

公开(公告)日：2016-10-20

申请号：US15197509

申请日：2016-06-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre MORIN ,  Nicolas LOUBET

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.