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1.发明授权公开(公告)号：US11115038B2
公开(公告)日：2021-09-07
申请号：US16923335
申请日：2020-07-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Bruno Gailhard , Laurent Truphemus , Christophe Eva
Abstract: The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.
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2.发明申请公开(公告)号：US20190245377A1
公开(公告)日：2019-08-08
申请号：US16267968
申请日：2019-02-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Laurent Truphemus , Sebastien Ortet
CPC classification number: H02J9/005 , G06F1/263 , G06F1/30 , G11C5/14 , G11C5/141 , G11C11/40 , G11C11/4074 , G11C16/30
Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.
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公开(公告)号：US08854135B2
公开(公告)日：2014-10-07
申请号：US13752538
申请日：2013-01-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Michel Cuenca , Laurent Truphemus
CPC classification number: H03F3/45076 , H03F1/086 , H03F3/45192 , H03F3/45771 , H03F2200/36 , H03F2200/447 , H03F2203/45322 , H03F2203/45391 , H03F2203/45392 , H03F2203/45471
Abstract: An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product.
Abstract translation: 运算放大器可以包括差分级，其包括两个晶体管，其栅极分别连接到运算放大器的两个输入端。 两个晶体管的源极可以连接到其传递的电流取决于温度变化的第一电流源以及传递的电流与绝对温度成比例的第二电流源。 这两个电流的总和可能不太依赖于温度，因为两个晶体管与两个电流源的源极的这个连接分别通过两个电阻器实现，并且通过两个晶体管的电流是 施加与温度类型成比例的，以便在获得与温度无关的恒定增益带宽积的同时，允许基本上温度独立地消除运算放大器的偏移电压。
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Patent Agency Ranking
4.发明申请公开(公告)号：US20210391744A1
公开(公告)日：2021-12-16
申请号：US17459465
申请日：2021-08-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Laurent Truphemus , Sebastien Ortet
Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.
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公开(公告)号：US20130207720A1
公开(公告)日：2013-08-15
申请号：US13752538
申请日：2013-01-29
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Michel CUENCA , Laurent Truphemus
IPC: H03F3/45
CPC classification number: H03F3/45076 , H03F1/086 , H03F3/45192 , H03F3/45771 , H03F2200/36 , H03F2200/447 , H03F2203/45322 , H03F2203/45391 , H03F2203/45392 , H03F2203/45471
Abstract: An operational amplifier may include a differential stage comprising two transistors whose gates are respectively linked to the two inputs of the operational amplifier. The sources of the two transistors may be linked to a first current source whose delivered current depends negatively on temperature variations and to a second current source whose delivered current is proportional to absolute temperature. The sum of these two currents may be less dependent on temperature, in that this link of the sources of the two transistors with the two current sources is effected respectively by way of two resistors, and in that the current which passes through the two transistors is imposed of proportional with temperature type, so as to allow substantially temperature-independent elimination of the offset voltage of the operational amplifier while obtaining a temperature-independent constant gain-bandwidth product.
Abstract translation: 运算放大器可以包括差分级，其包括两个晶体管，其栅极分别连接到运算放大器的两个输入端。 两个晶体管的源极可以连接到其传递的电流取决于温度变化的第一电流源以及传递的电流与绝对温度成比例的第二电流源。 这两个电流的总和可能不太依赖于温度，因为两个晶体管与两个电流源的源极的这个连接分别通过两个电阻器实现，并且通过两个晶体管的电流是 施加与温度类型成比例的，以便在获得与温度无关的恒定增益带宽积的同时，允许基本上温度独立地消除运算放大器的偏移电压。
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6.发明授权公开(公告)号：US11670956B2
公开(公告)日：2023-06-06
申请号：US17459465
申请日：2021-08-27
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Laurent Truphemus , Sebastien Ortet
CPC classification number: H02J9/005 , G06F1/263 , G06F1/30 , G11C5/141 , G11C11/4074 , G11C16/30 , G11C5/14 , G11C11/40
Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.
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7.发明授权公开(公告)号：US11245405B2
公开(公告)日：2022-02-08
申请号：US17352849
申请日：2021-06-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Bruno Gailhard , Laurent Truphemus , Christophe Eva
Abstract: A start-up phase of a phase lock loop (PLL) circuit includes supplying, by a phase comparator, of control pulses during which an output signal frequency of an oscillator increases. The increase includes an application of a pre-charge current at the oscillator input. A determination is made of a time variation of the output signal frequency. At least one adjustment is made of the intensity of the pre-charge current depending on the at least one determined time variation so as to approach a reference time variation.
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8.发明授权公开(公告)号：US11139676B2
公开(公告)日：2021-10-05
申请号：US16267968
申请日：2019-02-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Laurent Truphemus , Sebastien Ortet
Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.
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