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1.发明授权公开(公告)号：US11942935B2
公开(公告)日：2024-03-26
申请号：US17861067
申请日：2022-07-08
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Mark Wallis , Jean-Francois Link , Joran Pantel
IPC: H03K19/17724 , H03K19/173 , H03K19/17736 , H03K19/20
CPC classification number: H03K19/17724 , H03K19/1737 , H03K19/1774 , H03K19/17744 , H03K19/20
Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.
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公开(公告)号：US20170288918A1
公开(公告)日：2017-10-05
申请号：US15629257
申请日：2017-06-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mark Wallis , Yoann Bouvet , Pierre Demaj
CPC classification number: H04B3/54 , H04L5/0007 , H04L25/03993 , H04L25/067 , H04L27/2607 , H04L27/2656 , H04L27/2675 , H04L27/2691
Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.
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公开(公告)号：US11979153B2
公开(公告)日：2024-05-07
申请号：US17733934
申请日：2022-04-29
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Jean-Francois Link , Mark Wallis , Joran Pantel
IPC: H03K19/17736 , H03K19/173
CPC classification number: H03K19/17744 , H03K19/1737 , H03K19/1774
Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.
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公开(公告)号：US10050672B2
公开(公告)日：2018-08-14
申请号：US15629257
申请日：2017-06-21
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mark Wallis , Yoann Bouvet , Pierre Demaj
Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.
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5.发明申请公开(公告)号：US20170272105A1
公开(公告)日：2017-09-21
申请号：US15617831
申请日：2017-06-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mark Wallis
CPC classification number: H04B1/0007 , H04B3/54 , H04B2203/5425 , H04L5/001
Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.
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Patent Agency Ranking
公开(公告)号：US11855633B2
公开(公告)日：2023-12-26
申请号：US17827515
申请日：2022-05-27
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Jean-Francois Link , Mark Wallis , Joran Pantel
IPC: H03K19/17724 , H03K19/173 , H03K19/17704 , H03K3/0233 , H03K19/096
CPC classification number: H03K19/17724 , H03K3/0233 , H03K19/096 , H03K19/1737 , H03K19/17708
Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.
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公开(公告)号：US20230359368A1
公开(公告)日：2023-11-09
申请号：US18192237
申请日：2023-03-29
Applicant: STMicroelectronics(Rousset) SAS
Inventor： Mark Wallis , Laurent Lestringand
IPC: G06F3/06
CPC classification number: G06F3/0622 , G06F3/0637 , G06F3/0673
Abstract: In accordance with an embodiment, a system-on-chip includes: a memory circuit comprising a first memory region accessible with a first access right level and a second memory region accessible with the first access right level or a second access right level, at least one first peripheral having the first access right level, at least one second peripheral having the second access right level; and a direct memory access circuit configured to generate direct memory accesses, wherein the direct memory access circuit includes at least one first direct memory access controller having the first access right level and at least one second direct memory access controller having the second access right level.
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公开(公告)号：US11204739B2
公开(公告)日：2021-12-21
申请号：US16599581
申请日：2019-10-11
Inventor： Mark Wallis , Yannick Sebillet
Abstract: A microcontroller is capable of executing a process that is parameterizable by at least one parameter. The microcontroller includes a processor and a hardware module coupled to the processor. The hardware module is configured to hardware execute the process and the processor is configured to deliver the at least one parameter to the hardware module.
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9.发明授权公开(公告)号：US09979418B2
公开(公告)日：2018-05-22
申请号：US15617831
申请日：2017-06-08
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mark Wallis
CPC classification number: H04B1/0007 , H04B3/54 , H04B2203/5425 , H04L5/001
Abstract: A method includes digital/analog conversion of a digital signal modulated by information to provide a modulated initial analog signal having a crest factor greater than one, and amplification of the initial analog signal to provide an amplified modulated signal. A modulated channel analog signal derived from the modulated amplified analog signal is transmitted over a communications channel, with impedance of the communications channel varying during the transmission. The method further includes at least one determination during the transmission of a peak-clipping rate of the amplified analog signal over at least one time interval, and an adjustment of a level of the initial analog signal as a function of the determined peak-clipping rate.
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公开(公告)号：US09729199B2
公开(公告)日：2017-08-08
申请号：US14984966
申请日：2015-12-30
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Mark Wallis , Yoann Bouvet , Pierre Demaj
CPC classification number: H04B3/54 , H04L5/0007 , H04L25/03993 , H04L25/067 , H04L27/2607 , H04L27/2656 , H04L27/2675 , H04L27/2691
Abstract: A method is for processing an analog signal coming from a transmission channel. The analog signal may include a useful signal modulated on a sub-set of carriers. The method may include analog-to-digital converting of the analog signal into a digital signal, and synchronization processing the digital signal. The synchronizing may include determining, in a time domain, a limited number of coefficients of a predictive filter from an autoregressive model of the digital signal, and filtering the digital signal in the time domain by a digital finite impulse response filter with coefficients based upon the limited number of coefficients to provide a filtered digital signal. The method may include detecting of an indication allowing a location in the frame structure to be identified, using the filtered digital signal and a reference signal.
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