公开(公告)号：US20200076437A1

公开(公告)日：2020-03-05

申请号：US16674207

申请日：2019-11-05

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin GUPTA ,  Nitin JAIN

IPC: H03L1/00 ,  H03L7/183 ,  H03L7/087

Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

公开(公告)号：US20130343137A1

公开(公告)日：2013-12-26

申请号：US14014208

申请日：2013-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Siddharth GUPTA ,  Nitin JAIN ,  Anand Kumar MISHRA

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。

公开(公告)号：US20200235702A1

公开(公告)日：2020-07-23

申请号：US16703250

申请日：2019-12-04

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36 ,  H03B5/06

Abstract: A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.

公开(公告)号：US20190334509A1

公开(公告)日：2019-10-31

申请号：US15962089

申请日：2018-04-25

Applicant: STMicroelectronics International N.V.

Inventor： Nitin GUPTA ,  Nitin JAIN

IPC: H03K3/354 ,  H03L5/00

Abstract: A ring oscillator circuit is formed by series connected inverter circuits with a feedback loop. The inverter circuits are source biased with an oscillator voltage. A resistor-less bias current generator circuit generates a bias current for application to a replica inverter circuit to generate a bias voltage. A scaling circuit operates to scale the bias voltage by a selectable scaling factor to generate the oscillator voltage in a manner which balances a mobility effect of the inverter circuits within the ring oscillator circuit against a threshold voltage effect of the inverter circuits within the ring oscillator circuit. The clock signal output from the ring oscillator circuit has a frequency which is independent of process, voltage and temperature (PVT) spread.

公开(公告)号：US20230421101A1

公开(公告)日：2023-12-28

申请号：US18463212

申请日：2023-09-07

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B2200/0082

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US20230412155A1

公开(公告)日：2023-12-21

申请号：US18323998

申请日：2023-05-25

Applicant: STMicroelectronics International N.V.

Inventor： Nitin JAIN ,  Anand KUMAR ,  Kallol CHATTERJEE

IPC: H03K3/03 ,  H03K3/012 ,  H03K3/354

CPC classification number: H03K3/0307 ,  H03K3/3545 ,  H03K3/012

Abstract: A low power crystal oscillator circuit has a high power part and a low power part. Crystal oscillation is initialized using the high power part. An automatic amplitude control circuit includes a current subtractor that decreases current in the high power part as an amplitude of the crystal oscillation increases. A current limiting circuit may limit current in the low power part in order to further reduce power consumption by the low power crystal oscillator circuit. Additionally, an automatic amplitude detection circuit may turn off the high power part after the amplitude of the crystal oscillation reaches a predetermined level in order to further reduce power consumption of the low power crystal oscillator circuit, and may turn back on the high power part after the amplitude of the crystal oscillation reaches a second predetermined level in order to maintain the crystal oscillation.

公开(公告)号：US20230090782A1

公开(公告)日：2023-03-23

申请号：US17931863

申请日：2022-09-13

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36

Abstract: A low power crystal oscillator circuit having a high power part and a low power part. Oscillation is initialized using the high power part. Once the crystal is under stable oscillation, the circuit switches to the low power part and continue operation for a long duration.

公开(公告)号：US20140300386A1

公开(公告)日：2014-10-09

申请号：US14231026

申请日：2014-03-31

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Nitin JAIN ,  Nitin GUPTA

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: A level shifting circuit includes a first inverter including a pair of transistors of opposite conductivity type, the first inverter adapted to receive an input signal in a first voltage domain and further including at least one additional transistor driven by a voltage in a second voltage domain. A second inverter is coupled in series with the first inverter and operable to generate an output signal in the second voltage domain. The second inverter includes a pair of transistors of opposite conductivity type, and further includes at least one additional transistor driven by a voltage in the first voltage domain. The additional transistors are operable to approximately equalize the fall times of output signals generated by the first and second inverters.

Abstract translation: 电平移位电路包括第一反相器，其包括具有相反导电类型的一对晶体管，第一反相器适于接收第一电压域中的输入信号，并且还包括由第二电压域中的电压驱动的至少一个附加晶体管。 第二反相器与第一反相器串联耦合并且可操作以在第二电压域中产生输出信号。 第二反相器包括一对相反导电类型的晶体管，并且还包括由第一电压域中的电压驱动的至少一个附加晶体管。 附加晶体管可操作以近似均衡由第一和第二逆变器产生的输出信号的下降时间。