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公开(公告)号：US11637562B2
公开(公告)日：2023-04-25
申请号：US17677511
申请日：2022-02-22
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Roberto Modaffari , Paolo Pesenti , Germano Nicollini
Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
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公开(公告)号：US11199422B2
公开(公告)日：2021-12-14
申请号：US17125599
申请日：2020-12-17
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Matteo Quartiroli , Alessandro Mecchia , Paolo Pesenti , Stefano Facchinetti , Andrea Donadel
IPC: G01C25/00 , G01C19/5776 , H04L27/22
Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.
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公开(公告)号：US10900805B2
公开(公告)日：2021-01-26
申请号：US15919882
申请日：2018-03-13
Applicant: STMicroelectronics S.r.l.
Inventor： Matteo Quartiroli , Alessandro Mecchia , Paolo Pesenti , Stefano Facchinetti , Andrea Donadel
IPC: G01C25/00 , G01C19/5776 , H04L27/22
Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.
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公开(公告)号：US20210102822A1
公开(公告)日：2021-04-08
申请号：US17125599
申请日：2020-12-17
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Matteo Quartiroli , Alessandro Mecchia , Paolo Pesenti , Stefano Facchinetti , Andrea Donadel
IPC: G01C25/00 , G01C19/5776 , H04L27/22
Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.
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公开(公告)号：US10648813B2
公开(公告)日：2020-05-12
申请号：US15919874
申请日：2018-03-13
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Mecchia , Matteo Quartiroli , Paolo Pesenti
IPC: G01C19/5776 , G01C19/5712 , H04L27/38 , B81B7/00
Abstract: A demodulator demodulates an in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value having an integer part and a fractional part. A noise-shaping modulator generates a succession of quantized values of integer type, the quantized values having a mean equal to the phase calibration value. A generating stage generates a demodulating signal phase locked with the input signal, the demodulating signal having a phase which depends linearly on the quantized values. A demodulating stage demodulates the input signal by means of the demodulating signal.
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Patent Agency Ranking
公开(公告)号：US11984860B2
公开(公告)日：2024-05-14
申请号：US17839335
申请日：2022-06-13
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto Modaffari , Paolo Pesenti , Mario Maiore , Tiziano Chiarillo
CPC classification number: H03F3/70 , G01R27/2605 , H03F3/45968 , H03F2200/375
Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.
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公开(公告)号：US10794772B2
公开(公告)日：2020-10-06
申请号：US15957999
申请日：2018-04-20
Applicant: STMicroelectronics S.r.l.
Inventor： Michele Vaiana , Paolo Pesenti , Mario Chiricosta , Calogero Marco Ippolito , Mario Maiore
Abstract: A circuit includes a first input terminal, a second input terminal, a third input terminal and an output terminal. A first summation node adds signals at the first and third input terminals. A second summation node subtracts signals at the second and third input terminals. A selector selects between the added signals and subtracted signals in response to a selection signal. The output of the selector is integrated to generate an integrated signal. The integrated signal is compared by a comparator to a threshold, the comparator generating an output signal at the output terminal having a first level and a second level. Feedback of the output signal produces the selection signal causing the selector to select the added signals in response to the first level of the output signal and causing the selector to select the subtracted signals in response to the second level of the output signal.
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公开(公告)号：US12101104B2
公开(公告)日：2024-09-24
申请号：US17721110
申请日：2022-04-14
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Roberto Modaffari , Paolo Pesenti
IPC: H03M3/00
Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.
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公开(公告)号：US11290124B2
公开(公告)日：2022-03-29
申请号：US17163230
申请日：2021-01-29
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Roberto Modaffari , Paolo Pesenti , Germano Nicollini
IPC: H03M3/00
Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
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10.发明申请公开(公告)号：US20180274941A1
公开(公告)日：2018-09-27
申请号：US15919882
申请日：2018-03-13
Applicant: STMicroelectronics S.r.l.
Inventor： Matteo Quartiroli , Alessandro Mecchia , Paolo Pesenti , Stefano Facchinetti , Andrea Donadel
IPC: G01C25/00 , G01C19/5776
CPC classification number: G01C25/005 , G01C19/5776
Abstract: A demodulator for demodulating the in-phase component of an input signal which is in-phase and quadrature modulated. The demodulator includes a register storing a phase calibration value and a temperature sensor that performs a plurality of temperature sensings. A compensating stage generates for each temperature sensed a corresponding first sample on the basis of the difference between the sensed temperature and a calibration temperature and a compensation function indicative of a relationship existing between the phase of the input signal and the temperature. A combination stage generates a plurality of second samples, each second sample being a function of the phase calibration value and a corresponding first sample. A generating stage generates a demodulating signal having a phase which depends on the second samples and a demodulating stage demodulates the input signal by means of the demodulating signal.
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