-
公开(公告)号：US11637562B2
公开(公告)日：2023-04-25
申请号：US17677511
申请日：2022-02-22
摘要： A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
-
公开(公告)号：US09954501B2
公开(公告)日：2018-04-24
申请号：US15156155
申请日：2016-05-16
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F3/3027 , H03F3/45183 , H03F3/45475 , H03F3/45659 , H03F2200/129 , H03F2203/45008 , H03F2203/45112 , H03F2203/45134 , H03F2203/45418 , H03F2203/45601
摘要： An amplifier includes a first input branch and a second input branch that form a differential input stage and a current mirror connected to the differential input. The current mirror is governed as a function of a common mode feedback signal applied to a control node of the current mirror. A second, amplification, stage includes a branch flowing through which is a current, which is a function of the current that flows in the first input branch, and is in turn connected to a first output branch. A capacitive element is coupled between the control node and the second stage. The circuit is symmetrical with respect to the input stage.
-
公开(公告)号：US10056892B2
公开(公告)日：2018-08-21
申请号：US15394472
申请日：2016-12-29
CPC分类号： H03K5/2481 , G01R19/0038 , H03F3/45179 , H03F3/45273 , H03K3/0377 , H03K5/24
摘要： A comparator circuit including: a first node and a second node, which receive a first current and a second current, respectively; a first current mirror, which includes a first load transistor and a first output transistor; and a second current mirror, which includes a second load transistor and a second output transistor. The comparator circuit further includes: a first feedback transistor and a second feedback transistor cross-coupled together, the control terminals of the first and second feedback transistors being connected to the first and second nodes, respectively; a first resistor, having a first terminal, which is connected to the control terminal of the first load transistor, and a second terminal, which is connected to the first node and to the control terminal of the first output transistor; and a second resistor, having a first terminal, connected to the control terminal of the second load transistor, and a second terminal, connected to the second node and to the control terminal of the second output transistor.
-
4.发明申请NINETY-DEGREE PHASE SHIFTER CIRCUIT AND CORRESPONDING NINETY-DEGREE PHASE-SHIFTING METHOD 审中-公开NINETY-DEGREE相位更换电路和相应的NINETY-DEGREE相位移动方法公开(公告)号：US20170019087A1
公开(公告)日：2017-01-19
申请号：US15053176
申请日：2016-02-25
CPC分类号： H03H11/18 , G01C19/5776 , G01C25/005 , H03H2210/043
摘要： A phase shifter, which carries out a ninety-degree phase shift of a sinusoidal input signal having an input frequency, at the same input frequency, envisages: a continuous-time all-pass filter stage, which receives the sinusoidal input signal and generates an output signal phase-shifted by 90° at a phase-shift frequency that is a function of a RC time constant of the all-pass filter stage; and a calibration stage, which is coupled to the all-pass filter stage and generates a calibration signal for the all-pass filter stage, such that the phase-shift frequency is equal to the input frequency of the sinusoidal input signal, irrespective of variations of the value of the input frequency and/or of the RC time constant with respect to a nominal value.
摘要翻译： 在相同输入频率下执行具有输入频率的正弦输入信号的九十度相移的移相器设想：连续时间全通滤波器级，其接收正弦输入信号并产生 输出信号在全通滤波器级的RC时间常数的函数的相移频率相移90°; 以及校准级，其耦合到全通滤波器级并且产生用于全通滤波器级的校准信号，使得相移频率等于正弦输入信号的输入频率，而不管变化如何 相对于标称值的输入频率的值和/或RC时间常数。
-
公开(公告)号：US11984860B2
公开(公告)日：2024-05-14
申请号：US17839335
申请日：2022-06-13
CPC分类号： H03F3/70 , G01R27/2605 , H03F3/45968 , H03F2200/375
摘要： A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.
-
公开(公告)号：US11658625B2
公开(公告)日：2023-05-23
申请号：US17141812
申请日：2021-01-05
发明人： Roberto Modaffari
CPC分类号： H03F3/45197 , H03K5/24 , H03F2200/375
摘要： A preamplifier circuit comprises a first pair of transistors and a second pair of transistors having current flow paths therethrough coupled at first and second output nodes and providing first and second current flow lines intermediate a supply node and ground. The two pairs of transistors comprise: first and second input transistors located intermediate the outputs nodes and one of the supply node and ground providing respective input nodes, first and second load transistors intermediate the output nodes and the other of the supply node and ground. The load transistors have control terminals capacitively coupled to the other of the supply node and ground and a reset switch arrangement is provided periodically activatable to short the first output node, the second output node as well as the control terminals of the first load transistor and the second load transistor.
-
公开(公告)号：US20210242846A1
公开(公告)日：2021-08-05
申请号：US17141812
申请日：2021-01-05
发明人： Roberto Modaffari
摘要： A preamplifier circuit comprises a first pair of transistors and a second pair of transistors having current flow paths therethrough coupled at first and second output nodes and providing first and second current flow lines intermediate a supply node and ground. The two pairs of transistors comprise: first and second input transistors located intermediate the outputs nodes and one of the supply node and ground providing respective input nodes, first and second load transistors intermediate the output nodes and the other of the supply node and ground. The load transistors have control terminals capacitively coupled to the other of the supply node and ground and a reset switch arrangement is provided periodically activatable to short the first output node, the second output node as well as the control terminals of the first load transistor and the second load transistor.
-
公开(公告)号：US12101104B2
公开(公告)日：2024-09-24
申请号：US17721110
申请日：2022-04-14
发明人： Roberto Modaffari , Paolo Pesenti
IPC分类号： H03M3/00
摘要： A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.
-
公开(公告)号：US11716061B2
公开(公告)日：2023-08-01
申请号：US17665399
申请日：2022-02-04
CPC分类号： H03F3/45273 , H03F3/45269 , H03F2203/45526
摘要： A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.
-
公开(公告)号：US11290124B2
公开(公告)日：2022-03-29
申请号：US17163230
申请日：2021-01-29
IPC分类号： H03M3/00
摘要： A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
-
-
-
-
-
-
-
-
-
搜索结果
12 条记录 (耗时 0.017 秒)
