公开(公告)号：US10468306B2

公开(公告)日：2019-11-05

申请号：US15942540

申请日：2018-04-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L21/8234 ,  H01L21/02 ,  H01L23/52 ,  H01L27/088 ,  H01L21/48 ,  H01L29/66 ,  H01L27/092 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  B82Y40/00 ,  H01L21/311

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

公开(公告)号：US10804112B2

公开(公告)日：2020-10-13

申请号：US15979147

申请日：2018-05-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  B81C1/00 ,  H01L21/321

Abstract: A planarization structure is formed with a planar upper face enclosing a relief projecting from a planar substrate. The process used deposits a layer of a first material over the reliefs and then forms a layer of a second material with a planar upper face. This second material may be etched selectively with respect to the first material. The second layer is processed so that the protuberances of the first material are uncovered. A planarizing is then performed on the first material as far as the layer of the second material by selective chemical-mechanical polishing with respect to the second material.

公开(公告)号：US10998236B2

公开(公告)日：2021-05-04

申请号：US16582576

申请日：2019-09-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L21/8234 ,  H01L21/02 ,  H01L23/52 ,  H01L27/088 ,  H01L21/48 ,  H01L29/06 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/775 ,  B82Y40/00 ,  H01L21/311

Abstract: A strip made of a semiconductor material is formed over a substrate. Longitudinal portions of the strip having a same length are covered with sacrificial gates made of an insulating material and spaced apart from each other. Non-covered portions of the strip are doped to form source/drain regions. An insulating layer followed by a layer of a temporary material is then deposited. Certain ones of the sacrificial gates are left in place. Certain other ones of the sacrificial gates are replaced by a metal gate structure. The temporary material is then replaced with a conductive material to form contacts to the source/drain regions.

公开(公告)号：US10026821B2

公开(公告)日：2018-07-17

申请号：US15467082

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.

公开(公告)号：US20180061955A1

公开(公告)日：2018-03-01

申请号：US15467082

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic Gaben

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853

Abstract: An all-around gate field-effect transistor includes two drain-source areas supported by a semiconductor substrate. At least one channel region, surrounded with a gate insulated by a gate insulator, extends between the two drain-source areas. The at least one channel region is located above an insulating layer resting on the substrate and positioned between the two drain-source areas. This insulating layer has a thickness-to-permittivity ratio at least 2 times greater than that of the gate insulator. An extension of the insulating layer is positioned to insulate at least one of the channel regions from the semiconductor substrate.