公开(公告)号：US20190207014A1

公开(公告)日：2019-07-04

申请号：US16228032

申请日：2018-12-20

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud REGNIER ,  Dann MORILLON ,  Franck JULIEN ,  Marjorie HESSE

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/66568 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/78654

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US20250040165A1

公开(公告)日：2025-01-30

申请号：US18911058

申请日：2024-10-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud REGNIER ,  Dann MORILLON ,  Franck JULIEN ,  Marjorie HESSE

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A MOS transistor including a substrate, a conductive having lateral walls, drain and source regions, and spacers having an upper surface such that the spacers are buried in the substrate and are position between the conductive gate and the drain and source regions is provided. The spacers are each cuboid-shaped and have a width that is constant along the spacers height and independent from a height of the conductive gate. A device including the MOS transistor and a method of manufacture for producing a right-hand portion and a left-hand portion of a MOS transistor is also provided.

公开(公告)号：US20230223448A1

公开(公告)日：2023-07-13

申请号：US18094023

申请日：2023-01-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Christian RIVERO ,  Franck JULIEN

IPC: H01L29/40 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L29/401 ,  H01L29/456 ,  H01L21/76843 ,  H01L21/76858 ,  H01L23/53266 ,  H01L23/5226

Abstract: A method of manufacturing a radio frequency switch includes the steps of: forming a first silicide layer on a second conductive or semiconductor layer; forming a third insulating layer on the first layer; forming a cavity in the third insulating layer reaching the first silicide layer; forming a fourth metal layer in the cavity in contact with the first silicide layer; performing a non-oxidizing annealing; and filling the cavity with a conductive material. The first silicide layer is provided on one or more of the gate, source, and drain of a transistor forming the radio frequency switch.

公开(公告)号：US20240063280A1

公开(公告)日：2024-02-22

申请号：US18230423

申请日：2023-08-04

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck JULIEN ,  Julien DELALLEAU ,  Julien DURA ,  Julien AMOUROUX ,  Stephane MONFRAY

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/7833 ,  H01L29/42368 ,  H01L29/401

Abstract: A MOSFET transistor includes, on a semiconductor layer, a stack of a gate insulator and of a gate region on the gate insulator. The gate region has a first gate portion and a second gate portion between the first gate portion and the gate insulator. The first gate portion has a first length in a first lateral direction of the transistor. The second gate portion has a second length in the first lateral direction that is shorter than the first length.

公开(公告)号：US20230378295A1

公开(公告)日：2023-11-23

申请号：US18197909

申请日：2023-05-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Siddhartha DHAR ,  Stephane MONFRAY ,  Alain FLEURY ,  Franck JULIEN

IPC: H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/40

CPC classification number: H01L29/42368 ,  H01L27/088 ,  H01L21/823462 ,  H01L29/401

Abstract: A transistor includes a semiconductor layer with a stack of a gate insulator and a conductive gate on the semiconductor layer. A thickness of the gate insulator is variable in a length direction of the transistor. The gate insulator includes a first region having a first thickness below a central region of the conductive gate. The gate insulator further includes a second region having a second thickness, greater than the first thickness, below an edge region of conductive gate.

公开(公告)号：US20210175346A1

公开(公告)日：2021-06-10

申请号：US17180197

申请日：2021-02-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud REGNIER ,  Dann MORILLON ,  Franck JULIEN ,  Marjorie HESSE

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/786 ,  H01L29/417 ,  H01L21/28 ,  H01L21/84 ,  H01L29/78

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US20210036126A1

公开(公告)日：2021-02-04

申请号：US16939767

申请日：2020-07-27

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien Delalleau ,  Franck JULIEN

IPC: H01L29/66 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/027 ,  H01L29/78

Abstract: In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.

公开(公告)号：US20240154034A1

公开(公告)日：2024-05-09

申请号：US18386159

申请日：2023-11-01

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Julien DURA ,  Franck JULIEN ,  Julien AMOUROUX ,  Stephane MONFRAY

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/84 ,  H01L27/1203

Abstract: A transistor includes a source region, a drain region and a body region arranged in a semiconductor layer. A gate region tops the body region. The body region includes a first doped layer and a second layer between the first doped layer and the gate region. The second layer is an epitaxial layer that is less heavily doped than the first doped layer.

公开(公告)号：US20230012522A1

公开(公告)日：2023-01-19

申请号：US17935754

申请日：2022-09-27

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Franck JULIEN ,  Stephan NIEL ,  Leo GAVE

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/66

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.

公开(公告)号：US20210159318A1

公开(公告)日：2021-05-27

申请号：US17100559

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Franck JULIEN ,  Stephan NIEL ,  Leo GAVE

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/51

Abstract: A method for manufacturing an electronic device includes locally implanting ionic species into a first region of a silicon nitride layer and into a first region of an electrically insulating layer located under the first region of the silicon nitride layer. A second region of the silicon nitride layer and a region of the electrically insulating layer located under the second region of the silicon nitride layer are protected from the implantation. The electrically insulating layer is disposed between a semi-conducting substrate and the silicon nitride layer. At least one trench is formed extending into the semi-conducting substrate through the silicon nitride layer and the electrically insulating layer. The trench separates the first region from the second region of the electrically insulating layer. The electrically insulating layer is selectively etched, and the etch rate of the electrically insulating layer in the first region is greater than the etch rate in the second region.