-
公开(公告)号：US20210367619A1
公开(公告)日：2021-11-25
申请号：US17394118
申请日：2021-08-04
Inventor： Fabrice ROMAIN , Mathieu LISART , Patrick ARNOULD
Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
-
公开(公告)号：US20210067177A1
公开(公告)日：2021-03-04
申请号：US17010351
申请日：2020-09-02
Inventor： Fabrice ROMAIN , Mathieu LISART , Patrick Arnould
Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.
-
3.发明申请公开(公告)号：US20190279947A1
公开(公告)日：2019-09-12
申请号：US16292958
申请日：2019-03-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI , Mathieu LISART
Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
-
公开(公告)号：US20210065834A1
公开(公告)日：2021-03-04
申请号：US17010400
申请日：2020-09-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice ROMAIN , Mathieu LISART
Abstract: A method for detecting a writing error of a datum in memory includes: storing at least two parts of equal size of a binary word representative of said datum at the same address in at least two identical memory circuits, and comparing internal control signals of the two memory circuits to determine existence of the writing error.
-
公开(公告)号：US20190385957A1
公开(公告)日：2019-12-19
申请号：US16436747
申请日：2019-06-10
Inventor： Mathieu LISART , Bruce RAE
IPC: H01L23/00 , H01L23/552
Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
-
Patent Agency Ranking
6.发明申请公开(公告)号：US20190103369A1
公开(公告)日：2019-04-04
申请号：US16208253
申请日：2018-12-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Christian RIVERO , Pascal FORNARA , Guilhem BOUTON , Mathieu LISART
IPC: H01L23/00 , H01L21/311 , H01L23/528 , H01L23/522 , H01L27/088 , H01L21/768 , H01L23/58 , H01L21/8234
Abstract: An integrated circuit includes a semiconductor substrate and a multitude of electrically conductive pads situated between component zones of the semiconductor substrate and a first metallization level of the integrated circuit, respectively. The multitude of electrically conductive pads are encapsulated in an insulating region and include: first pads, in electrical contact with corresponding first component zones, and at least one second pad, not in electrical contact with a corresponding second component zone.
-
公开(公告)号：US20150194393A1
公开(公告)日：2015-07-09
申请号：US14667232
申请日：2015-03-24
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Mathieu LISART , Sylvie WUIDART , Alexandre SARAFIANOS
CPC classification number: H01L23/576 , G06F21/75 , H01L22/14 , H01L22/30 , H01L22/34 , H01L2924/0002 , Y10T307/76 , H01L2924/00
Abstract: An integrated circuit, including: a semiconductor substrate of a first conductivity type; a plurality of regions of the first conductivity type vertically extending from the surface of the substrate, each of the regions being laterally delimited all along its periphery by a region of the second conductivity type; and a device for detecting a variation of the substrate resistance between each region of the first conductivity type and an area for biasing the substrate to a reference voltage.
Abstract translation: 一种集成电路，包括：第一导电类型的半导体衬底; 所述第一导电类型的多个区域从所述基板的表面垂直延伸，每个所述区域沿着其外围沿着所述第二导电类型的区域横向界定; 以及用于检测第一导电类型的每个区域和用于将衬底偏压的区域之间的衬底电阻变化为参考电压的装置。
-
公开(公告)号：US20220310192A1
公开(公告)日：2022-09-29
申请号：US17839168
申请日：2022-06-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Fabrice ROMAIN , Mathieu LISART
Abstract: A method for detecting a reading error of a datum in memory. A binary word which is representative of the datum and an error correcting or detecting code is read by: reading a first part of the binary word stored at a first address in a first memory circuit; and reading a second part of the binary word stored at a second address in a second memory circuit. The first and second parts read from the first and second memory circuits, respectively, are concatenated to form a read binary word. The datum is then obtained by removing the error correcting or detecting code from the read binary word. A new error correcting or detecting code is calculated from the obtained datum and compared to the removed error correcting or detecting code to detect error in the obtained datum.
-
公开(公告)号：US20210313280A1
公开(公告)日：2021-10-07
申请号：US17351930
申请日：2021-06-18
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Abderrezak MARZAKI , Mathieu LISART
Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.
-
公开(公告)号：US20210183792A1
公开(公告)日：2021-06-17
申请号：US17166156
申请日：2021-02-03
Inventor： Mathieu LISART , Bruce RAE
IPC: H01L23/00
Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.026 seconds)
