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公开(公告)号：US11818883B2
公开(公告)日：2023-11-14
申请号：US17540029
申请日：2021-12-01
CPC分类号： H10B20/367 , G11C16/0466 , H01L23/57
摘要： The present description concerns a ROM including at least one first rewritable memory cell.
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公开(公告)号：US10833027B2
公开(公告)日：2020-11-10
申请号：US15784883
申请日：2017-10-16
IPC分类号： G01L23/00 , H01L23/00 , H04L9/32 , H04L9/00 , G06F9/4401 , H01L21/265 , H01L21/266 , H01L21/3205 , H01L21/8234 , H01L23/528 , H01L27/088 , H03K17/14
摘要： An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
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公开(公告)号：US10186491B2
公开(公告)日：2019-01-22
申请号：US15606212
申请日：2017-05-26
IPC分类号： H01L23/00 , H01L21/768 , H01L23/522
摘要： An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
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公开(公告)号：US20180102328A1
公开(公告)日：2018-04-12
申请号：US15606212
申请日：2017-05-26
IPC分类号： H01L23/00 , H01L23/522 , H01L21/768
CPC分类号： H01L23/573 , H01L21/76802 , H01L21/76831 , H01L23/522 , H01L23/5226
摘要： An integrated circuit chip includes an interconnection stack with a cavity formed therein. The cavity extends through one or more interconnection levels of the stack. A material at least partially fills the cavity. The fill material has a selectivity to polishing and/or to etching different by more than 10% from a selectivity to polishing and/or to etching of a material forming an insulator of the interconnection stack.
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公开(公告)号：US12063775B2
公开(公告)日：2024-08-13
申请号：US18484906
申请日：2023-10-11
CPC分类号： H10B20/367 , G11C16/0466 , H01L23/57
摘要： The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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公开(公告)号：US20240040781A1
公开(公告)日：2024-02-01
申请号：US18484906
申请日：2023-10-11
IPC分类号： H10B20/00
CPC分类号： H10B20/367 , H01L23/57
摘要： The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.
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公开(公告)号：US10754618B2
公开(公告)日：2020-08-25
申请号：US16035798
申请日：2018-07-16
IPC分类号： G06F7/58 , H01L21/768 , G06F21/70 , H04L9/08
摘要： A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
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公开(公告)号：US20190034168A1
公开(公告)日：2019-01-31
申请号：US16035798
申请日：2018-07-16
IPC分类号： G06F7/58 , G06F21/70 , H01L21/768
CPC分类号： G06F7/588 , G06F21/70 , H01L21/76829 , H04L9/0866
摘要： A random number generation device includes conductive lines including interruptions and a number of conductive vias. A via is located at each interruption. Each via randomly fills or does not fill the interruption. A circuit is capable of determining the electric continuity or lack of continuity of the conductive lines.
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公开(公告)号：US20220199632A1
公开(公告)日：2022-06-23
申请号：US17540029
申请日：2021-12-01
IPC分类号： H01L27/112
摘要： The present description concerns a ROM including at least one first rewritable memory cell.
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公开(公告)号：US20180277496A1
公开(公告)日：2018-09-27
申请号：US15784883
申请日：2017-10-16
IPC分类号： H01L23/00 , H01L27/088 , H01L23/528 , H03K17/14 , H01L21/8234 , H01L21/265 , H01L21/266 , H01L21/3205 , G06F9/44
摘要： An integrated device for physically unclonable functions is based on a set of MOS transistors exhibiting a random distribution of threshold voltages which are obtained by lateral implantations of dopants exhibiting non-predictable characteristics, resulting from implantations through a polysilicon layer. A certain number of these transistors form a group of gauge transistors which makes it possible to define a mean gate source voltage making it possible to bias the gates of certain others of these transistors (which are used to define the various bits of the unique code generated by the function). All these transistors consequently exhibit a random distribution of drain-source currents and a comparison of each drain-source current of a transistor associated with a bit of the digital code with a reference current corresponding to the average of this distribution makes it possible to define the logical value 0 or 1 of this bit.
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