LDO OVERSHOOT PROTECTION
    1.
    发明申请

    公开(公告)号:US20210278868A1

    公开(公告)日:2021-09-09

    申请号:US16810639

    申请日:2020-03-05

    Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.

    LDO overshoot protection in a cascaded architecture

    公开(公告)号:US11703897B2

    公开(公告)日:2023-07-18

    申请号:US16810639

    申请日:2020-03-05

    CPC classification number: G05F1/56

    Abstract: In an embodiment, a method includes: receiving a main supply voltage; generating a first regulated output voltage with a DC-DC converter; providing the main supply voltage to a driver of a control terminal of an output transistor of an LDO; receiving, at an input terminal of the LDO, the first regulated output voltage; generating, at an output terminal of the LDO, a second regulated output voltage from the first regulated output voltage; and when the main supply voltage falls below a predetermined threshold, discharging a capacitor coupled to the input terminal of the LDO by activating a switch coupled to the input terminal of the LDO.

    Electronic Switching Device with Reduction of Leakage Currents and Corresponding Control Method

    公开(公告)号:US20170222639A1

    公开(公告)日:2017-08-03

    申请号:US15490356

    申请日:2017-04-18

    CPC classification number: H03K17/161 G11C27/024 H03K3/012 H03K17/6872

    Abstract: A method is used to control an electronic device that includes a switching unit having a main MOS transistor having a substrate, a first conducting electrode and a second conducting electrode coupled to an output terminal. The method includes controlling the main transistor in such a way as to put it into an on state or an off state such that, when the main transistor is in the on state, the substrate and the first conducting electrode of the main transistor are connected to an input terminal and, when the main transistor is in the off state, the first conducting electrode of the main transistor is isolated from the input terminal and a first bias voltage is applied to the first conducting electrode and a second bias voltage is applied to the substrate of the main transistor.

    DIGITAL-TO-ANALOG CONVERTER AND CORRESPONDING DIGITAL-TO-ANALOG CONVERSION METHOD

    公开(公告)号:US20240097701A1

    公开(公告)日:2024-03-21

    申请号:US18463844

    申请日:2023-09-08

    CPC classification number: H03M1/70

    Abstract: One embodiment provides a digital-to-analog converter that includes an output amplifier configured to be powered with a controllable power supply voltage and a ground reference voltage. The output amplifier is configured to generate an analog output signal having a dynamic range centered on a common-mode voltage. The output amplifier includes a common-mode adaptation circuit configured to position a level of the common-mode voltage at a level located in a middle portion of an interval of voltages located between the power supply voltage and the ground reference voltage, according to an effective level of the power supply voltage.

    OSCILLATOR
    7.
    发明申请

    公开(公告)号:US20220166415A1

    公开(公告)日:2022-05-26

    申请号:US17524306

    申请日:2021-11-11

    Abstract: Series of first ramps and second ramps are generated. A circuit delivers a first signal representative of the comparison of each first ramp with a set point and delivers a second signal representative of the comparison of each second ramp with the set point. Based on the first and second signals: a first ramp is stopped and a second ramp is started when the first ramp reaches the set point, and a second ramp is stopped and a first ramp is started when the second ramp reaches the set point. The value of the set point is modulated in response a maximum value of the first/second last ramp compared with the set point.

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