SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER CIRCUIT WITH DATA SHARING FOR POWER SAVING

    公开(公告)号:US20230099514A1

    公开(公告)日:2023-03-30

    申请号:US17940236

    申请日:2022-09-08

    Abstract: A continuous time, sigma-delta analog-to-digital converter circuit includes a sigma-delta modulator circuit configured to receive an analog input signal. A single bit quantizer of the modulator generates a digital output signal at a sampling frequency. A data storage circuit stores bits of the digital output signal and digital-to-analog converter (DAC) elements are actuated in response to the stored bits to generate an analog feedback signal for comparison to the analog input signal. A filter circuit includes polyphase signal processing paths and a summation circuit configured to sum outputs from the polyphase signal processing paths to generate a converted output signal. A fan out circuit selectively applies the stored bits from the data storage circuit to inputs of the polyphase signal processing paths of the filter circuit.

    ON CHIP TEST ARCHITECTURE FOR CONTINUOUS TIME DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER

    公开(公告)号:US20220345149A1

    公开(公告)日:2022-10-27

    申请号:US17723225

    申请日:2022-04-18

    Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

    FLIP-FLOP WITH SELF CORRECTION
    4.
    发明公开

    公开(公告)号:US20240356549A1

    公开(公告)日:2024-10-24

    申请号:US18632137

    申请日:2024-04-10

    Inventor: Abhishek JAIN

    CPC classification number: H03K19/00338 H03K3/0372 H03K3/0375

    Abstract: A radiation hardened flip-flop includes a plurality of secondary flip-flops. Each secondary flip-flop includes both a data input terminal and an alternate data input terminal. Each secondary flip-flop also includes an enable terminal that selectively enables use of the alternate data input terminal. The radiation hardened flip-flop includes an error detection circuit that detects whether an error is present in one or more of the secondary flip-flops and provides an enable signal to the enable terminals indicating the presence or absence of an error in one or more of the secondary flip-flops.

    ON CHIP TEST ARCHITECTURE FOR CONTINUOUS TIME DELTA SIGMA ANALOG-TO-DIGITAL CONVERTER

    公开(公告)号:US20240235573A1

    公开(公告)日:2024-07-11

    申请号:US18396542

    申请日:2023-12-26

    CPC classification number: H03M3/378 H03M3/46 H03M3/496

    Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

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