公开(公告)号：US11892360B2

公开(公告)日：2024-02-06

申请号：US17136240

申请日：2020-12-29

Applicant: STMicroelectronics International N.V.

Inventor： Atul Dwivedi ,  Pijush Kanti Panja

IPC: G01K7/00 ,  H03K17/60

CPC classification number: G01K7/00 ,  H03K17/60 ,  G01K2219/00

Abstract: Circuitry generates base-to-emitter voltages (Vbe1, Vbe2) of two BJTs biased at different current densities, a base-to-emitter voltage (Vbe) of a BJT biased so Vbe is complementary to absolute temperature and has a curved non-linearity across temperature, and base-to-emitter voltages (Vbe1_c, Vbe2_c) of two BJTs biased by a temperature independent constant current and a current proportional to absolute temperature so Vbe2_c−Vbe1_c has the same but opposite curved non-linearity across temperature as Vbe. A sampling circuit samples these voltages and provides them to inputs of a loop filter. Filter outputs are quantized to produce a bitstream. The sampling circuit: when the received bit of the bitstream is zero, causes integration of Vbe1−Vbe2 to produce a voltage proportional to absolute temperature (αΔVbe); and when the received bit of the bitstream is one, causes integration of Vbe2_c−Vbe_Vbe1_c to produce a negative voltage complementary to absolute temperature −Vbe_c without non-linearity across temperature.

公开(公告)号：US20150200632A1

公开(公告)日：2015-07-16

申请号：US14153119

申请日：2014-01-13

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Rajesh Yadav

IPC: H03F1/30 ,  H03F3/45 ,  H03K17/687

CPC classification number: H03K17/687 ,  H03F3/45183 ,  H03F3/45753 ,  H03F2200/447 ,  H03F2203/45341 ,  H03K3/3565 ,  H03K5/2481

Abstract: A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.

Abstract translation: 将在第一晶体管处接收的第一信号与在第二晶体管处接收的第二信号进行比较，考虑滞后值以产生比较输出。 第一和第二晶体管中的至少一个具有浮动体积。 开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮动体。 设置滞后值的第三和第四输入信号在第三和第四晶体管处被接收，并被比较以产生差分输出。 第三和第四晶体管中的至少一个具有浮动体积。 差分放大器确定用于施加到第三和第四晶体管中的至少一个的浮动体的差分输出之间的差异，并进一步用作第一和第二体偏置电压之一。

公开(公告)号：US11867572B2

公开(公告)日：2024-01-09

申请号：US17521123

申请日：2021-11-08

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Kallol Chatterjee ,  Atul Dwivedi

IPC: H03K17/14 ,  G01K7/14 ,  G01K7/01 ,  H03K19/018 ,  H03M1/12

CPC classification number: G01K7/14 ,  G01K7/01 ,  H03K17/14 ,  H03K19/018 ,  H03M1/1245

Abstract: A temperature sensing circuit a switched capacitor circuit selectively samples ΔVbe and Vbe voltages and provides the sampled voltages to inputs of an integrator. A quantization circuit quantizes outputs of the integrator to produce a bitstream. When a most recent bit of the bitstream is a logic zero, operation includes sampling and integration of ΔVbe a first given number of times to produce a voltage proportional to absolute temperature. When the most recent bit of the bitstream is a logic one, operation includes cause sampling and integration of Vbe a second given number of times to produce a voltage complementary to absolute temperature. A low pass filter and decimator filters and decimates the bitstream produced by the quantization circuit to produce a signal indicative of a temperature of a chip into which the temperature sensing circuit is placed.

公开(公告)号：US09432015B2

公开(公告)日：2016-08-30

申请号：US14153119

申请日：2014-01-13

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Rajesh Yadav

IPC: H03K5/22 ,  H03K17/687 ,  H03F3/45 ,  H03K5/24 ,  H03K3/3565

CPC classification number: H03K17/687 ,  H03F3/45183 ,  H03F3/45753 ,  H03F2200/447 ,  H03F2203/45341 ,  H03K3/3565 ,  H03K5/2481

Abstract: A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.

Abstract translation: 将在第一晶体管处接收的第一信号与在第二晶体管处接收的第二信号进行比较，考虑滞后值以产生比较输出。 第一和第二晶体管中的至少一个具有浮动体积。 开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮动体。 设置滞后值的第三和第四输入信号在第三和第四晶体管处被接收，并被比较以产生差分输出。 第三和第四晶体管中的至少一个具有浮动体积。 差分放大器确定用于施加到第三和第四晶体管中的至少一个的浮动体的差分输出之间的差异，并进一步用作第一和第二体偏置电压之一。

公开(公告)号：US12209919B1

公开(公告)日：2025-01-28

申请号：US18406551

申请日：2024-01-08

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Kallol Chatterjee ,  Atul Dwivedi

IPC: H02K17/14 ,  G01K7/01 ,  H03K17/14 ,  H03K19/003 ,  H03M1/12

Abstract: A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. The bitstream is filtered and decimated to produce an output code representative of the temperature of the chip.

公开(公告)号：US11775001B2

公开(公告)日：2023-10-03

申请号：US17467985

申请日：2021-09-07

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Gautam Dey Kanungo

IPC: G05F3/26

CPC classification number: G05F3/267

Abstract: A reference current generator circuit generating a reference current that is proportional to absolute temperature as a function of a difference between bias voltages of first and second transistors. A voltage generator generates an input voltage from the reference current by applying the reference current that is proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, with the input voltage being generated at a node between given adjacent ones of the plurality of transistors. The input voltage is complementary to absolute temperature. A differential amplifier is biased by a current derived from the reference current and generates a temperature insensitive output reference voltage from the input voltage and a voltage proportional to absolute temperature.

公开(公告)号：US11137788B2

公开(公告)日：2021-10-05

申请号：US16558717

申请日：2019-09-03

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Gautam Dey Kanungo

IPC: G05F3/26

Abstract: A sub-bandgap reference voltage generator includes a reference current generator generating a reference current (proportional to absolute temperature), a voltage generator generating an input voltage (proportional to absolute temperature) from the reference current, and a differential amplifier. The differential amplifier is biased by the reference current and has an input receiving the input voltage and a resistor generating a voltage proportional to absolute temperature summed with the input voltage to produce a temperature insensitive output reference voltage. The reference current generator may generate the reference current as a function of a difference between bias voltages of first and second transistors. The voltage generator may generate the input voltage by applying the current proportional to absolute temperature through a plurality of transistors coupled in series between the bias voltage of the second transistor and ground, and tapping a node between given adjacent ones of the plurality of transistors.