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    Schmitt trigger in FDSOI technology
    2.
    发明授权
    Schmitt trigger in FDSOI technology 有权
    施密特触发器采用FDSOI技术

    公开(公告)号：US09306550B2

    公开(公告)日：2016-04-05

    申请号：US14216719

    申请日：2014-03-17

    Applicant: STMicroelectronics International N.V.

    Inventor： Ravinder Kumar

    IPC: H03K3/3565

    CPC classification number: H03K3/3565

    Abstract: A Schmitt Trigger is implemented in FDSOI technology. The Schmitt Trigger includes a first inverting stage having an NMOS and PMOS transistor having their drains tied together. The NMOS and PMOS transistor each have a first gate coupled to the input voltage and a back gate coupled to the output of the Schmitt Trigger.

    Abstract translation: 施密特触发器采用FDSOI技术实现。 施密特触发器包括具有连接在一起的NMOS和PMOS晶体管的第一反相级。 NMOS和PMOS晶体管各自具有耦合到输入电压的第一栅极和耦合到施密特触发器的输出的后栅极。

    Driver circuit including driver transistors with controlled body biasing
    3.
    发明授权
    Driver circuit including driver transistors with controlled body biasing 有权
    驱动电路包括具有受控体偏置的驱动晶体管

    公开(公告)号：US09473135B2

    公开(公告)日：2016-10-18

    申请号：US14500076

    申请日：2014-09-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

    IPC: H03K3/00 ,  H03K17/687 ,  H03K19/0185

    CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

    Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

    Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

    Negative voltage tolerant IO circuitry for IO pad
    4.
    发明授权
    Negative voltage tolerant IO circuitry for IO pad 有权

    公开(公告)号：US10748890B2

    公开(公告)日：2020-08-18

    申请号：US15475270

    申请日：2017-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Ravinder Kumar

    IPC: H03K19/01 ,  H01L27/02 ,  H03K19/0175 ,  H01L29/78

    Abstract: Disclosed herein is an electronic device including an IO node, with a receiver coupled to receive input from the IO node. A transmitter driver has a first n-channel DMOS with a source coupled to the IO node. A pass gate circuit decouples the IO node from the receiver based upon presence of a negative voltage at the IO node and couples the IO node to the receiver based upon lack of presence of the negative voltage at the IO node. A transmit protection circuit applies the negative voltage from the IO node to the gate and bulk of the first n-channel DMOS based upon the presence of the negative voltage at the IO node.

    Level shifting circuit with conditional body biasing of transistors
    5.
    发明授权
    Level shifting circuit with conditional body biasing of transistors 有权

    公开(公告)号：US10355694B1

    公开(公告)日：2019-07-16

    申请号：US15961214

    申请日：2018-04-24

    Applicant: STMicroelectronics International N.V.

    Inventor： Ravinder Kumar

    IPC: H03K19/0185 ,  H03K19/20

    Abstract: A level shifting circuit receives a first input signal and complement of the first input signal as inputs and generates a level shifted first output signal and complement of the first output signal as outputs. The level shifting circuit includes a number of transistors that support body biasing. One set of body bias signals applied to certain ones of those transistors is generated as a function of the logical combination of the first input signal and the first output signal. Another set of body bias signals applied to certain other ones of those transistors is generated as a function of the logical combination of the complement of the first input signal and the complement of the first output signal. The conditional body bias applied to the transistors of the level shifting circuit makes the circuit operational for level shift at very low supply voltage levels.

    DRIVER CIRCUIT INCLUDING DRIVER TRANSISTORS WITH CONTROLLED BODY BIASING
    6.
    发明申请
    DRIVER CIRCUIT INCLUDING DRIVER TRANSISTORS WITH CONTROLLED BODY BIASING 有权
    驱动电路，包括带有控制的机身偏置的驱动器晶体管

    公开(公告)号：US20160094217A1

    公开(公告)日：2016-03-31

    申请号：US14500076

    申请日：2014-09-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Paras Garg ,  Rajesh Yadav ,  Saiyid Mohammad Irshad Rizvi ,  Ravinder Kumar

    IPC: H03K17/687

    CPC classification number: H03K17/687 ,  H03K19/0185 ,  H03K2217/0018

    Abstract: A drive circuit includes a first drive transistor coupled between a first supply node and an output pad of an integrated circuit and a second drive transistor coupled between a second supply node and the output pad. The first drive transistor and second drive transistors are controlled by a control signal. A body bias generator circuit is configured to apply a variable first body bias to the first transistor and a variable second body bias to the second transistor. The variable first and second body biases are generated as a function of the control signal and a voltage at the output pad.

    Abstract translation: 驱动电路包括耦合在集成电路的第一电源节点和输出焊盘之间的第一驱动晶体管，以及耦合在第二电源节点和输出焊盘之间的第二驱动晶体管。 第一驱动晶体管和第二驱动晶体管由控制信号控制。 体偏置发生器电路被配置为将可变第一体偏置施加到第一晶体管，并将可变第二体偏置施加到第二晶体管。 可变的第一和第二体偏置作为控制信号和输出焊盘处的电压的函数产生。

    NEGATIVE VOLTAGE TOLERANT IO CIRCUITRY FOR IO PAD
    7.
    发明申请
    NEGATIVE VOLTAGE TOLERANT IO CIRCUITRY FOR IO PAD 审中-公开

    公开(公告)号：US20180287379A1

    公开(公告)日：2018-10-04

    申请号：US15475270

    申请日：2017-03-31

    Applicant: STMicroelectronics International N.V.

    Inventor： Ravinder Kumar

    IPC: H02H11/00 ,  H03K19/0175 ,  H01L27/02 ,  H03K17/08

    Abstract: Disclosed herein is an electronic device including an IO node, with a receiver coupled to receive input from the IO node. A transmitter driver has a first n-channel DMOS with a source coupled to the IO node. A pass gate circuit decouples the IO node from the receiver based upon presence of a negative voltage at the IO node and couples the IO node to the receiver based upon lack of presence of the negative voltage at the IO node. A transmit protection circuit applies the negative voltage from the IO node to the gate and bulk of the first n-channel DMOS based upon the presence of the negative voltage at the IO node.

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