公开(公告)号：US20030218480A1

公开(公告)日：2003-11-27

申请号：US10407801

申请日：2003-04-04

Applicant: Indian ST (STMicroelectronics Pvt. Ltd.)

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/1774 ,  H03K19/17784

Abstract: An electronic circuit containing one or more digital synchronous sequential logic blocks at least one of which is either selected or deselected during operation. The electronic circuit includes an improved clock distribution scheme that reduces power consumption, comprising identifying means for determining the select/deselect state of each said deselectable synchronous sequential logic block, coupled to disabling means for disabling the clock input to each deselected synchronous sequential logic block.

Abstract translation: 一种包含一个或多个数字同步顺序逻辑块的电子电路，其中至少一个在操作期间被选择或取消选择。 电子电路包括一种降低功耗的改进的时钟分配方案，包括识别装置，用于确定每个所述可取消同步顺序逻辑块的选择/取消选择状态，耦合到禁用装置，用于禁止每个取消选择的同步顺序逻辑块的时钟输入。

公开(公告)号：US20040070422A1

公开(公告)日：2004-04-15

申请号：US10608854

申请日：2003-06-27

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Sushma Mohan ,  Parvesh Swami

IPC: H03K019/177

CPC classification number: H03K19/17728 ,  H03K19/1737

Abstract: A Programmable Logic Device (PLD) incorporating a plurality of Programmable Logic Blocks (PLBS) providing enhanced flexibility for Cascade logic functions, each comprising a multi-input Look Up Table (LUT) providing one input to a Cascade Logic block for implementing desired Cascade Logic functions. The other input of the Cascade Logic block is a Cascade-In signal. A 2-input selection multiplexer receives one input from the output of the Cascade Logic block and the other from the output of the LUT for selecting either the Cascade Logic output or the LUT output as the unregistered output. The arrangement is such that the Cascade output and the multiplexer output are simultaneously available from the PLB.

Abstract translation: 一种包含多个可编程逻辑块（PLBS）的可编程逻辑器件（PLD），其为级联逻辑功能提供增强的灵活性，每个逻辑器件包括多输入查找表（LUT），其为级联逻辑块提供一个输入，以实现所需的级联逻辑 功能。 级联逻辑块的另一个输入是级联输入信号。 2输入选择多路复用器从串级逻辑块的输出接收一个输入，而从LUT的输出接收另一个输入，用于选择级联逻辑输出或LUT输出作为未注册输出。 这种布置使得级联输出和多路复用器输出可以从PLB同时获得。

公开(公告)号：US20040015758A1

公开(公告)日：2004-01-22

申请号：US10436895

申请日：2003-05-13

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Shalini Pathak ,  Parvesh Swami

IPC: G01R031/28

CPC classification number: G11C29/025 ,  G01R31/318516 ,  G11C29/02 ,  G11C29/12

Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

Abstract translation: 可编程逻辑器件（PLD）能够独立地或在配置期间测试配置存储器。 PLD可以包括用于选择配置存储器阵列的特定列或行的选择器，以及用于存储需要存储在所选列或行中的配置数据的输入数据存储装置，或用于测试所选列或行的测试数据 。 PLD还可以包括用于存储来自所选择的列或行的输出的输出数据存储装置以及提供用于验证配置存储器阵列的数据线的正确操作的控制信号而不干扰存储在存储器中的数据的测试逻辑 数组。

公开(公告)号：US20040008055A1

公开(公告)日：2004-01-15

申请号：US10449750

申请日：2003-05-29

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

IPC: H03K019/177

CPC classification number: H03K19/1776 ,  H03K3/012 ,  H03K3/037 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17784

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract translation: 一种可编程逻辑器件，用于为顺序逻辑和数据存储功能提供功率消耗降低，包括至少一个电路装置，其可配置为在电路时钟选定的一个或两个边缘上工作的双边沿触发触发器。

公开(公告)号：US20030214321A1

公开(公告)日：2003-11-20

申请号：US10407802

申请日：2003-04-04

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K019/173

CPC classification number: H03K19/17736

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

Abstract translation: 一种改进的可编程逻辑设备架构，其通过在设备中的任何其他PLB上访问任何可编程逻辑块（PLB）的域中的定义的电路元件来提供资源的更有效的利用，通过在路由结构中并入选择性地连接 将PLB域中的电路元件的输入或输出连接到将所有PLB连接在一起的公共互连矩阵。