公开(公告)号：US20030155611A1

公开(公告)日：2003-08-21

申请号：US10378198

申请日：2003-03-03

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Michel Marty ,  Helene Baudry

IPC: H01L029/76

CPC classification number: H01L29/66242 ,  H01L29/66272

Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.

Abstract translation: 该制造工艺包括产生具有非本征基极和本征基极的基极区域的相位，以及产生发射极区域的相位，该发射极区域包括位于位于本征基底之上的发射极窗口中的较窄的下部的发射极阵列。 外在基底的制造包括在发射器窗口被限定之后进行的掺杂剂的注入，在距离发射器窗口的横向边界的任一侧和预定距离dp处，以便相对于该发射极自对准 窗口，并且在发射极块形成之前。

公开(公告)号：US20030098493A1

公开(公告)日：2003-05-29

申请号：US10272444

申请日：2002-10-16

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Francois Leverd ,  Philippe Coronel ,  Joaquin Torres

IPC: H01L021/8238 ,  H01L029/00

CPC classification number: H01L21/76229 ,  H01L21/764

Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Abstract translation: 在半导体衬底中形成的隔离沟具有侧壁和底壁。 隔板在侧壁上并且彼此面对以在它们之间形成狭窄的通道。 底壁和间隔物涂覆有用于限定通道中的封闭空腔的电绝缘材料。 隔离沟槽适用于集成电路的制造。

公开(公告)号：US20020014676A1

公开(公告)日：2002-02-07

申请号：US09898540

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Helene Baudry ,  Francois Leverd

IPC: H01L029/00

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/763

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract translation: 在制造晶体管之前，在衬底中形成深绝缘沟槽的相位之后是在衬底中形成浅绝缘沟槽并延伸深沟槽的相位。 形成深沟槽的相位包括用初始氧化层涂覆深沟槽的内壁，并且在由绝缘材料形成的封套内的硅填充深沟槽。 形成浅沟槽的相位包括用初始氧化层涂覆浅沟槽的内壁，并用绝缘材料填充浅沟槽。

公开(公告)号：US20010051413A1

公开(公告)日：2001-12-13

申请号：US09796116

申请日：2001-02-28

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Michel Marty ,  Helene Baudry

IPC: H01L021/331

CPC classification number: H01L29/66242

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract translation: 该方法包括在半导体衬底的基极区域上依次形成多晶Ge或多晶硅层，在Ge或SiGe层的选定区域上的蚀刻停止层，相同的多晶硅层 导电类型作为基极区，然后是外层介电材料。 蚀刻层包括在停止层处停止以形成发射器窗预制件，去除停止膜并选择性地去除发射器窗预制件中的Ge或SiGe层以形成发射极窗并形成由导电性的多晶硅制成的发射极 键入窗口中的基础区域的相反。

公开(公告)号：US20020003286A1

公开(公告)日：2002-01-10

申请号：US09930084

申请日：2001-08-15

Applicant: STMICROELECTRONICS S.A.

Inventor： Michel Marty ,  Alain Chantre ,  Jorge Regolini

IPC: H01L029/70

CPC classification number: H01L29/66242 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/7378

Abstract: The vertical bipolar transistor includes an SiGe heterojunction base formed by a stack of layers of silicon and silicon-germanium resting on an initial layer of silicon nitride extending over a side insulation region surrounding the upper part of the intrinsic collector. The stack of layers also extends on the surface of the intrinsic collector which lies inside a window formed in the initial layer of silicon nitride.

Abstract translation: 垂直双极晶体管包括SiGe异质结基底，其由沉积在围绕本征收集器的上部的侧绝缘区域延伸的氮化硅初始层上的硅层和硅锗叠层形成。 层叠层还在固有收集器的位于形成于初始氮化硅层的窗口内部的表面上延伸。