公开(公告)号：US20030155611A1

公开(公告)日：2003-08-21

申请号：US10378198

申请日：2003-03-03

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Michel Marty ,  Helene Baudry

IPC: H01L029/76

CPC classification number: H01L29/66242 ,  H01L29/66272

Abstract: The fabrication process comprises a phase of producing a base region having an extrinsic base and an intrinsic base, and a phase of producing an emitter region comprising an emitter block having a narrower lower part located in an emitter window provided above the intrinsic base. Production of the extrinsic base comprises implantation of dopants, carried out after the emitter window has been defined, on either side of and at a predetermined distance dp from the lateral boundaries of the emitter window so as to be self-aligned with respect to this emitter window, and before the emitter block is formed.

Abstract translation: 该制造工艺包括产生具有非本征基极和本征基极的基极区域的相位，以及产生发射极区域的相位，该发射极区域包括位于位于本征基底之上的发射极窗口中的较窄的下部的发射极阵列。 外在基底的制造包括在发射器窗口被限定之后进行的掺杂剂的注入，在距离发射器窗口的横向边界的任一侧和预定距离dp处，以便相对于该发射极自对准 窗口，并且在发射极块形成之前。

公开(公告)号：US20010053584A1

公开(公告)日：2001-12-20

申请号：US09817898

申请日：2001-03-26

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Didier Dutartre ,  Helene Baudry

IPC: H01L021/76

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract translation: 具有异质结基底的自对准双多晶硅型双极晶体管包括位于半导体衬底的有源区上方的半导体异质结区域和界定有源区域的隔离区域，以及掺入晶体管的本征基极区域。 位于有源区上方并与半导体异质结区的上表面接触的发射极区。 形成晶体管的非本征基极区域的多晶硅层，位于发射极区域的每一侧，并且通过分离层与半导体异质结区域分离，所述分离层包括位于发射极区域正前方的导电连接部分。 该连接部件确保外部基座和内部基座之间的电接触。

公开(公告)号：US20020185657A1

公开(公告)日：2002-12-12

申请号：US10097651

申请日：2002-03-13

Applicant: STMICROELECTRONICS S.A.

Inventor： Alain Chantre ,  Helene Baudry ,  Didier Dutartre

IPC: H01L031/0328

CPC classification number: H01L29/66242 ,  H01L29/7378

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract translation: 晶体管和双晶硅异质结基极型双极晶体管的制造方法，其中具有SiGe异质结的半导体层通过非选择性外延在衬底的有源区和围绕有源区的绝缘区形成。 在有源区域的一部分上方的半导体层上形成至少一个阻挡层。 在半导体层和停止层的一部分上形成多晶硅层和上绝缘层，留下发射器窗口。 发射极区域通过在发射极窗中外延形成，部分地搁置在上绝缘层上并与半导体层接触。

公开(公告)号：US20020014676A1

公开(公告)日：2002-02-07

申请号：US09898540

申请日：2001-07-03

Applicant: STMicroelectronics S.A.

Inventor： Michel Marty ,  Helene Baudry ,  Francois Leverd

IPC: H01L029/00

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/763

Abstract: Prior fabricating the transistors, a phase of forming a deep insulative trench in the substrate is followed by a phase of forming a shallow insulative trench in the substrate and extending the deep trench. The phase of forming the deep trench includes coating the inside walls of the deep trench with an initial oxide layer and filling the deep trench with silicon inside an envelope formed from an insulative material. The phase of forming the shallow trench includes coating the inside walls of the shallow trench with an initial oxide layer and filling the shallow trench with an insulative material.

Abstract translation: 在制造晶体管之前，在衬底中形成深绝缘沟槽的相位之后是在衬底中形成浅绝缘沟槽并延伸深沟槽的相位。 形成深沟槽的相位包括用初始氧化层涂覆深沟槽的内壁，并且在由绝缘材料形成的封套内的硅填充深沟槽。 形成浅沟槽的相位包括用初始氧化层涂覆浅沟槽的内壁，并用绝缘材料填充浅沟槽。

公开(公告)号：US20010051413A1

公开(公告)日：2001-12-13

申请号：US09796116

申请日：2001-02-28

Applicant: STMicroelectronics S.A.

Inventor： Alain Chantre ,  Michel Marty ,  Helene Baudry

IPC: H01L021/331

CPC classification number: H01L29/66242

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

Abstract translation: 该方法包括在半导体衬底的基极区域上依次形成多晶Ge或多晶硅层，在Ge或SiGe层的选定区域上的蚀刻停止层，相同的多晶硅层 导电类型作为基极区，然后是外层介电材料。 蚀刻层包括在停止层处停止以形成发射器窗预制件，去除停止膜并选择性地去除发射器窗预制件中的Ge或SiGe层以形成发射极窗并形成由导电性的多晶硅制成的发射极 键入窗口中的基础区域的相反。