-
公开(公告)号：US20210183442A1
公开(公告)日：2021-06-17
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
-
2.发明申请公开(公告)号：US20190214079A1
公开(公告)日：2019-07-11
申请号：US16227438
申请日：2018-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
-
公开(公告)号：US20190043574A1
公开(公告)日：2019-02-07
申请号：US16155659
申请日：2018-10-09
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfré , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
-
公开(公告)号：US11289158B2
公开(公告)日：2022-03-29
申请号：US17123518
申请日：2020-12-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: An embodiment non-volatile memory device includes an array of memory cells, coupled to word lines, and a row decoder including a pull-down stage and a pull-up stage, which includes, for each word line: a corresponding control circuit, which generates a corresponding control signal; and a corresponding pull-up switch circuit, which is controlled via the control signal so as to couple/decouple the word line to/from the supply. The control circuit includes: a current mirror, which injects a current into an internal node; and a series circuit, which couples/decouples the corresponding internal node to/from ground, on the basis of selection/deselection of the corresponding word line so as to cause a decrease/increase in a voltage on the corresponding internal node. Each control signal is a function of the voltage on the corresponding internal node.
-
公开(公告)号：US11756614B2
公开(公告)日：2023-09-12
申请号：US17657861
申请日：2022-04-04
Applicant: STMicroelectronics S.r.l.
CPC classification number: G11C13/0004 , G11C7/02 , G11C7/06 , G11C13/004 , G11C13/0026 , G11C13/0028 , G11C13/0069
Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
-
Patent Agency Ranking
公开(公告)号：US11328768B2
公开(公告)日：2022-05-10
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
-
公开(公告)号：US20210193220A1
公开(公告)日：2021-06-24
申请号：US17119979
申请日：2020-12-11
Applicant: STMicroelectronics S.r.l.
Abstract: In an embodiment, the column decoder of a PCM device is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.
-
公开(公告)号：US10861543B2
公开(公告)日：2020-12-08
申请号：US16804698
申请日：2020-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: In one embodiment, a memory device includes a first sense amplifier, a second sense amplifier, a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier, a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier, a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier, a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier, a third lower switch arranged between a second lower main bit line to a second input of the first sense amplifier, and a third upper switch arranged between a second upper main bit line to a second input of the second sense amplifier.
-
公开(公告)号：US10658032B2
公开(公告)日：2020-05-19
申请号：US16155659
申请日：2018-10-09
Applicant: STMicroelectronics S.r.l.
Inventor： Cesare Torti , Fabio Enrico Carlo Disegni , Davide Manfré , Massimo Fidone
Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.
-
公开(公告)号：US10600479B2
公开(公告)日：2020-03-24
申请号：US16227438
申请日：2018-12-20
Applicant: STMicroelectronics S.r.l.
Inventor： Fabio Enrico Carlo Disegni , Cesare Torti , Davide Manfré
Abstract: A memory device including a first memory sector and a second memory sector, each of which includes a respective plurality of local bit lines, which may be selectively coupled to a plurality of main bit lines. The memory device further includes a first amplifier and a second amplifier, and a routing circuit, arranged between the main bit lines and the first and second amplifiers. The routing circuit includes: a first lower switch, arranged between a first lower main bit line and a first input of the first amplifier; a second lower switch, arranged between the first lower main bit line and a first input of the second amplifier; a first upper switch, arranged between a first upper main bit line and the first input of the first amplifier; and a second upper switch, arranged between the first upper main bit line and the first input of the second amplifier. The second inputs of the first and second amplifiers are coupled to a second lower main bit line and to a second upper main bit line, respectively.
-
-
-
-
-
-
-
-
-
Search Results
10
records
(took 0.011 seconds)
