公开(公告)号：US20220190816A1

公开(公告)日：2022-06-16

申请号：US17545719

申请日：2021-12-08

Applicant: STMicroelectronics S.r.l.

Inventor： Enrico CASTRO ,  Giovanni SUSINNA ,  Vincenzo RANDAZZO ,  Mirko DONDINI ,  Calogero Andrea TRECARICHI

IPC: H03K17/082 ,  H02H9/02

Abstract: Current absorption management for an electronic fuse coupled between an electrical supply source node and an electrical load node selectively controls a high current electronic switch and a low current electronic switch coupled in parallel between the electrical supply source node and the electrical load node. The high current and low current electronic switches are alternatively actuated: in a first mode where the high current electronic switch is turned on and the low current electronic switch is turned off, and in a second mode where the high current electronic switch is turned off and the low current electronic switch is turned on. Change to the second mode may be made in response to a standby state or a sensing of a lower current in the electrical load. Conversely, change to the first mode may be made in response to a sensing of a higher current in the electrical load.

公开(公告)号：US20180217952A1

公开(公告)日：2018-08-02

申请号：US15940650

申请日：2018-03-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Daniele MANGANO ,  Mirko DONDINI ,  Salvatore PISASALE

IPC: G06F13/28 ,  G06F3/06 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/067 ,  G06F13/4059 ,  G06F2213/0038

Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.

公开(公告)号：US20220065923A1

公开(公告)日：2022-03-03

申请号：US17406962

申请日：2021-08-19

Applicant: STMicroelectronics S.r.l.

Inventor： Mirko DONDINI ,  Roberto CRISAFULLI ,  Calogero Andrea TRECARICHI ,  Vincenzo RANDAZZO

IPC: G01R31/28

Abstract: An electronic device such as an e-fuse includes analog circuitry configured to be set to one or more self-test configurations. To that effect the device has self-test controller circuitry in turn including: an analog configuration and sensing circuit configured to set the analog circuitry to one or more self-test configurations and to sense test signals occurring in the analog circuitry set to such self-test configurations, a data acquisition circuit configured to acquire and convert to digital the test signals sensed at the analog sensing circuit, and a fault event detection circuit configured to check the test signals converted to digital against reference parameters. The device includes integrated therein a self-test controller configured to control parts or stages of the device to configure circuits, acquire data and control test execution under the coordination of a test sequencer.

公开(公告)号：US20200278711A1

公开(公告)日：2020-09-03

申请号：US16803942

申请日：2020-02-27

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Mirko DONDINI ,  Daniele MANGANO ,  Riccardo CONDORELLI

IPC: G05F1/575 ,  G06F1/10 ,  G06F13/40 ,  G05B19/042 ,  H03K19/17736 ,  H03B5/32

Abstract: An integrated circuit includes a clock control circuit coupled to a reference clock signal node and a plurality of circuits including a voltage regulator, a digital circuit, and an analog circuit. The voltage regulator, in operation, supplies a regulated voltage. The clock control circuit, in operation, generates a system clock. Input/output interface circuitry is coupled to the plurality of circuits and a common input/output node. The input/output interface circuitry, in operation, selectively couples one of the plurality of circuits to the common input/output node.

公开(公告)号：US20230187922A1

公开(公告)日：2023-06-15

申请号：US18064861

申请日：2022-12-12

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Vincenzo RANDAZZO ,  Alberto MARZO ,  Giovanni SUSINNA ,  Vanni POLETTO ,  Antoine PAVLIN ,  CalogeroAndrea TRECARICHI ,  Mirko DONDINI ,  Roberto CRISAFULLI ,  Enrico CASTRO ,  Romeo LETOR

IPC: H02H3/08 ,  H02H1/00 ,  H03K17/687 ,  H03K19/20

CPC classification number: H02H3/08 ,  H02H1/0007 ,  H03K17/687 ,  H03K19/20

Abstract: Embodiments are directed to electronic fuse devices and systems. One such electronic fuse includes current sensing circuitry that senses a current in a conductor coupled between a power supply and a load, and generates a current sensing signal indicative of the sensed current. I2t circuitry receives the current sensing signal and determines whether the sensed current exceeds an I2t curve of the conductor. The electronic fuse further includes at least one of external MOSFET temperature sensing circuitry that senses a temperature of an external MOSFET coupled to the conductor, low current bypass circuitry that supplies a reduced current to the load in a low power consumption mode during which the external MOSFET is in a non-conductive state, or desaturation sensing circuitry that senses a drain-source voltage of the external MOSFET.

公开(公告)号：US20180260585A1

公开(公告)日：2018-09-13

申请号：US15916067

申请日：2018-03-08

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mirko DONDINI ,  Gaetano DI STEFANO ,  Sergio ABENDA ,  Layachi DAINECHE

IPC: G06F21/85 ,  G06F21/71 ,  G06F13/40

CPC classification number: G06F21/85 ,  G06F13/4068 ,  G06F21/606 ,  G06F21/71 ,  G06F21/76

Abstract: An integrated circuit includes one or more intellectual property (IP) cores, one or more general purposes input/output (GPIO) interfaces, each GPIO interface having one or more ports, and one or more security circuits, each security circuit being coupled between an IP core and a GPIO interface. A security circuit, in operation, selectively enables communications between the IP core and the GPIO interface coupled to the security circuit based on an indication of the security status of the IP core, an indication of the security status of the GPIO interface or both the indication of the security status of the IP core and the indication of the security status of the GPIO interface.