公开(公告)号：US20240171424A1

公开(公告)日：2024-05-23

申请号：US18509618

申请日：2023-11-15

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GmbH ,  STMicroelectronics (Alps) SAS

Inventor： Fred Rennig ,  Giovanni Luca Torrisi ,  Manuel Gaertner ,  Philippe Sirito-Olivier ,  Fritz Burkhardt ,  Aldo Occhipinti

IPC: H04L12/40

CPC classification number: H04L12/40006 ,  H04L2012/40215

Abstract: A vehicle communication network includes electronic control units arranged in a plurality of groups. The electronic control units pertaining to the same group are coupled to each other via a respective dedicated communication bus. A central controller is coupled to the plurality of local controllers. Electrical loads are coupled to one of the electronic control units. Each of the electronic control units is configured to decode the received CAN frame to produce the actuation signal for a respective electrical load in response to a CAN frame being received from the respective local controller and transmit a CAN wake-up frame to the respective local controller and encode the feedback signal into a CAN frame for transmission to the respective local controller in response to the feedback signal being received from the respective electrical load.

公开(公告)号：US20240160598A1

公开(公告)日：2024-05-16

申请号：US18503744

申请日：2023-11-07

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Mirko Dondini ,  Calogero Andrea Trecarichi ,  Fred Rennig

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F2213/40

Abstract: An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.

公开(公告)号：US12259844B2

公开(公告)日：2025-03-25

申请号：US17829902

申请日：2022-06-01

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Application GMBH

Inventor： Giuseppe Cavallaro ,  Fred Rennig

IPC: G06F13/42 ,  G05B19/042 ,  G06F11/10 ,  G06F13/38 ,  G06F13/40

Abstract: In an embodiment a microcontroller includes a processing unit and a deserial-serial peripheral interface (DSPI) module, wherein the deserial-serial peripheral interface module is coupleable to a communication bus configured to operate according to a selected communication protocol, wherein the processing unit is configured to read user data intended for inclusion in an outgoing frame encoded according to the selected communication protocol, calculate, as a function of the user data, a cyclic redundancy check (CRC) value intended for inclusion in the outgoing frame, compose the outgoing frame by including the user data and the calculated CRC value into the outgoing frame, produce a DSPI frame encoded according to the selected communication protocol as a function of the outgoing frame and program a data register of the deserial-serial peripheral interface module with the DSPI frame, and wherein the deserial-serial peripheral interface module is configured to transmit the DSPI frame via the communication bus.

公开(公告)号：US20230300001A1

公开(公告)日：2023-09-21

申请号：US18174387

申请日：2023-02-24

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMicroelectronics S.r.l.

Inventor： Fred Rennig ,  Jochen Barthel ,  Ludek Beran ,  Mirko Dondini ,  Vaclav Dvorak ,  Vincenzo Polisi ,  Marianna Sanza' ,  CalogeroAndrea Trecarichi ,  Alfonso Furio

IPC: H04L12/40 ,  H03K19/00 ,  H03K17/687

CPC classification number: H04L12/40169 ,  H03K19/0002 ,  H03K17/6872 ,  H03K17/6874 ,  H04L12/40032 ,  H04L2012/40273 ,  H04L2012/40215

Abstract: In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.

公开(公告)号：US12047198B2

公开(公告)日：2024-07-23

申请号：US18320764

申请日：2023-05-19

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Rolf Nandlinger

IPC: H04L12/40 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4022 ,  G06F13/426 ,  H04L12/40169 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US20230267087A1

公开(公告)日：2023-08-24

申请号：US18309103

申请日：2023-04-28

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  G06F9/54

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G06F11/0772 ,  G06F11/0739 ,  H04L12/403 ,  G06F11/0757 ,  G05B19/042 ,  G06F9/542 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US11695589B2

公开(公告)日：2023-07-04

申请号：US17539936

申请日：2021-12-01

Applicant: STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Rolf Nandlinger

IPC: H04L12/40 ,  G06F13/40 ,  G06F13/42

CPC classification number: H04L12/40013 ,  G06F13/4022 ,  G06F13/426 ,  H04L12/40169 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: A device has a plurality of CAN XL communication systems, a bus, and a switching circuit. The bus has a transmission node and reception node, and receives from each CAN XL communication system a respective second transmission signal and drives the logic level at the transmission node as a function of the logic levels of the second transmission signals, and provides to each CAN XL communication system a respective second reception signal having a logic level determined as a function of the logic level at the reception node. The switching circuit supports a plurality of modes. In a first mode, the switching circuit is configured to provide the NRZ encoded transmission signals of the CAN XL communication systems as the second transmission signals to the bus system, and provide the respective second reception signal received from the bus to the CAN XL protocol controllers of the CAN XL communication system.

公开(公告)号：US20220318173A1

公开(公告)日：2022-10-06

申请号：US17806587

申请日：2022-06-13

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US10678726B2

公开(公告)日：2020-06-09

申请号：US16360229

申请日：2019-03-21

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GmbH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20240362176A1

公开(公告)日：2024-10-31

申请号：US18764940

申请日：2024-07-05

Applicant: STMicroelectronics Design & Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G05B19/042 ,  G06F9/54 ,  G06F11/07 ,  G06F11/10 ,  G06F13/40 ,  G06F13/42 ,  H03M13/09 ,  H04L12/40 ,  H04L12/403

CPC classification number: G06F13/362 ,  G05B19/042 ,  G06F9/542 ,  G06F11/0739 ,  G06F11/0757 ,  G06F11/0772 ,  G06F11/1004 ,  G06F13/4068 ,  G06F13/4282 ,  H04L12/40006 ,  H04L12/40013 ,  H04L12/40078 ,  H04L12/403 ,  G05B2219/1215 ,  G05B2219/2231 ,  G05B2219/31179 ,  H03M13/09 ,  H04L2012/40215

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.