-
公开(公告)号：US20230300001A1
公开(公告)日：2023-09-21
申请号：US18174387
申请日：2023-02-24
申请人： STMicroelectronics Application GMBH , STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. , STMicroelectronics S.r.l.
发明人： Fred Rennig , Jochen Barthel , Ludek Beran , Mirko Dondini , Vaclav Dvorak , Vincenzo Polisi , Marianna Sanza' , CalogeroAndrea Trecarichi , Alfonso Furio
IPC分类号： H04L12/40 , H03K19/00 , H03K17/687
CPC分类号： H04L12/40169 , H03K19/0002 , H03K17/6872 , H03K17/6874 , H04L12/40032 , H04L2012/40273 , H04L2012/40215
摘要： In an embodiment a processing system includes a sub-circuit including a three-state driver circuit, wherein the three-state driver circuit has a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal: in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch, in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch.
-
公开(公告)号：US20240160598A1
公开(公告)日：2024-05-16
申请号：US18503744
申请日：2023-11-07
IPC分类号： G06F13/42
CPC分类号： G06F13/4282 , G06F2213/40
摘要： An example processing system includes a processing circuit, a volatile memory and a CAN communication controller circuit. The CAN communication controller circuit includes configuration and status registers. A transmission handler circuit and a reception handler circuit transmits and receives data via the CAN core circuit by exchanging data with the volatile memory based on the configuration data stored to the configuration and status registers, and filter elements stored to the volatile memory. Specifically, the processing system further includes a hardware host circuit comprising a non-volatile memory configured to store first configuration data (CD1) and second configuration data (CD2). The CD1 includes configuration data to be transferred to the configuration and status registers of the CAN communication controller circuit and the CD2 includes at least one filter element to be transferred to the volatile memory. A control circuit manages an initialization mode, a reception mode and a transmission mode. During the initialization mode, the hardware host circuit stores the CD1 to the configuration and status registers and the CD2 to the volatile memory.
-
公开(公告)号：US10579561B2
公开(公告)日：2020-03-03
申请号：US15940650
申请日：2018-03-29
摘要： A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
-
公开(公告)号：US08990436B2
公开(公告)日：2015-03-24
申请号：US13904379
申请日：2013-05-29
CPC分类号： G06F9/466 , G06F13/1626 , G06F2213/0038
摘要： In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.
摘要翻译： 在一个实施例中，通过分配经过一致性检查的事务标识符来管理诸如片上系统（SoC）的系统的至少一个模块到诸如存储器的多个目标模块之一的访问事务。 如果已经为相同的给定目标模块发出了支票的输入标识符，则向相关标识符/给定目标模块对发送相同的输入标识符作为一致的输出标识符。 相反，如果相对于所述检查的所述输入标识符尚未被发布或者已经针对与所考虑的目标模块不同的目标模块已经被发布到相关标识符/给定目标模块对，则与输入标识符不同的新标识符 ，被分配为一致的输出标识符。
-
公开(公告)号：US10891399B2
公开(公告)日：2021-01-12
申请号：US15945177
申请日：2018-04-04
发明人： Mirko Dondini , Gaetano Di Stefano , Sergio Abenda
摘要： A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.
-
公开(公告)号：US10788870B2
公开(公告)日：2020-09-29
申请号：US16405086
申请日：2019-05-07
IPC分类号： G06F1/24 , G06F11/267 , H03K3/037
摘要： A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
-
7.发明申请公开(公告)号：US20140344485A1
公开(公告)日：2014-11-20
申请号：US14278403
申请日：2014-05-15
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.
摘要翻译： 通信系统被布置为将多个传输电路与互连网络接口。 每个传输电路产生读请求和/或写请求。 通信系统包括独立于互连网络的通信协议操作的第一电路。 特别地，第一电路包括：a）对于每个传输电路，配置用于从各个传输电路接收读取请求和/或写入请求的通信接口，b）分配电路，被配置为将读取请求 和/或将从所述传输电路接收的请求写入传输段，以及c）被配置为经由所述传送段的交织操作生成一系列段的交织电路。 通信系统还包括第二电路，其被配置为根据互连网络的协议将一系列段的传输段转换成数据包，并将数据包发送到互连网络。
-
公开(公告)号：US11644504B2
公开(公告)日：2023-05-09
申请号：US16791020
申请日：2020-02-14
IPC分类号： G01R31/3185 , G01R29/027 , G01R31/319 , G06F1/08 , G06F1/12 , G06F13/24
CPC分类号： G01R31/318552 , G01R29/0273 , G01R31/31922 , G01R31/318594 , G06F1/08 , G06F1/12 , G06F13/24
摘要： In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.
-
公开(公告)号：US20190354152A1
公开(公告)日：2019-11-21
申请号：US16405086
申请日：2019-05-07
IPC分类号： G06F1/24 , G06F11/267 , H03K3/037
摘要： A circuit includes a first node configured to receive a reset signal. A reset drive stage drives a reset node. The reset drive stage is coupled to the first node via a reset signal path to propagate the reset signal to the reset drive stage. The reset drive stage is activated as a result of assertion of a reset actuation state of the reset signal. A sensing node is coupled to the reset node via a signal sensing path. The sensing node is sensitive to a signal level of the reset node reaching a reset threshold. A reset signal hold circuit block is coupled to the first node and is configured to receive a reset command signal and assert the reset actuation state of the reset signal at the first node as a result of the reset command signal received.
-
公开(公告)号：US20180341791A1
公开(公告)日：2018-11-29
申请号：US15945177
申请日：2018-04-04
发明人： Mirko Dondini , Gaetano Di Stefano , Sergio Abenda
摘要： A system includes an intellectual property circuit; a general purpose input/output circuit coupled to the intellectual property circuit via a data path; and a switch coupled to the data path. The switch is activatable via a switch enable signal propagated on a switch enable path having a first end coupled to the intellectual property circuit and a second end coupled to the general purpose input/output circuit. The system further includes a secure link circuit coupled between the intellectual property circuit and the general purpose input/output circuit along the switch enable path. The secure link circuit is sensitive to security statuses of the intellectual property circuit and the general purpose input/output circuit, the secure link circuit being configured to admit propagation of the switch enable signal on the switch enable path in response to the intellectual property circuit and the general purpose input/output circuit having identical security statuses.
-
-
-
-
-
-
-
-
-
搜索结果
19 条记录 (耗时 0.018 秒)
